These d-c triggered multivibrators feature output pulse-duration control by three methods. The basic pulse time is programmed by selection of external resistance and capacitance values (see typical application data). The '122 and 'LS122 have internal timing resistors that allow the circuits to be used with only an external capacitor, if so desired. Once triggered, the basic pulse duration may be extended by retriggering the gated low-level-active (A) or high-level-active (B) inputs, or be reduced by use of the overriding clear. Figure 1 illustrates pulse control by retriggering and early clear.
The 'LS122 and 'LS123 are provided enough Schmitt hysteresis to ensure jitter-free triggering from the B input with transition rates as slow as 0.1 millivolt per nanosecond.
The Rint is nominally 10 k for '122 and 'LS122.
|Part number||Order||Technology Family||VCC (Min) (V)||VCC (Max) (V)||Bits (#)||Voltage (Nom) (V)||F @ nom voltage (Max) (MHz)||ICC @ nom voltage (Max) (mA)||tpd @ nom Voltage (Max) (ns)||IOL (Max) (mA)||IOH (Max) (mA)||Schmitt trigger||Rating||Operating temperature range (C)||Package Group|
||LS||4.75||5.25||2||5||35||20||56||8||-0.4||No||Catalog||0 to 70||
PDIP | 16
SOIC | 16
SO | 16
SSOP | 16
|SN54LS123||Samples not available||LS||4.75||5.25||2||5||35||20||56||8||-0.4||No||Military||-55 to 125||
CDIP | 16
CFP | 16
LCCC | 20