SN74LS266

ACTIVE

Quad 2-input exclusive-NOR gates with open collector outputs

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Product details

Parameters

Technology Family LS VCC (Min) (V) 4.75 VCC (Max) (V) 5.25 Channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 8 Input type Bipolar IOH (Max) (mA) 0 Output type Open-Collector Features High Speed (tpd 10-50ns) Data rate (Max) (Mbps) 35 Rating Catalog Operating temperature range (C) 0 to 70 open-in-new Find other XNOR (exclusive NOR) gate

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 open-in-new Find other XNOR (exclusive NOR) gate

Features

  • Can Be Used as a 4-Bit Digital Comparator
  • Input Clamping Diodes Simplify System Design
  • Fully Compatible with Most TTL Circuits

 

open-in-new Find other XNOR (exclusive NOR) gate

Description

The 'LS266 is comprised of four independent 2-input exclusive-NOR gates with open-collector outputs. The open-collector outputs permit tying outputs together for multiple-bit comparisons.

 

open-in-new Find other XNOR (exclusive NOR) gate
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Technical documentation

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Type Title Date
* Datasheet Quadruple 2-Input Exclusive-NOR Gates With Open-Collector Outputs datasheet Mar. 01, 1983
Technical articles How to keep your motor running safely Jun. 04, 2020
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Designing with the SN54/74LS123 (Rev. A) Mar. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SDLM039.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options

Ordering & quality

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