Product details

Technology Family LV-A Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Number of channels (#) 6 IOL (Max) (mA) 12 IOH (Max) (mA) 0 ICC (Max) (uA) 20 Input type Standard CMOS Output type Open-Drain Features Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Rating Catalog
Technology Family LV-A Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Number of channels (#) 6 IOL (Max) (mA) 12 IOH (Max) (mA) 0 ICC (Max) (uA) 20 Input type Standard CMOS Output type Open-Drain Features Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Rating Catalog
SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23 mm² 3.6 x 6.4
  • 2-V to 5.5-V VCC Operation
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode
    Operation
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 2500-V Human-Body Model
    • 200-V Machine Model
    • 2000-V Charged-Device Model
  • 2-V to 5.5-V VCC Operation
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode
    Operation
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 2500-V Human-Body Model
    • 200-V Machine Model
    • 2000-V Charged-Device Model

The SN74LV05A device contains six independent inverters designed for 2-V to 5.5-V VCC operation.

This device performs the Boolean function Y = A.

The SN74LV05A device contains six independent inverters designed for 2-V to 5.5-V VCC operation.

This device performs the Boolean function Y = A.

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Technical documentation

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Type Title Date
* Data sheet SN74LV05A Hex Inverters With Open-Drain Outputs datasheet (Rev. J) 22 Dec 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

In stock
Limit: 5
Simulation model

SN74LV05A IBIS Model

SCEM121.ZIP (9 KB) - IBIS Model
Simulation model

SN74LV05A Behavioral SPICE Model

SCLM191.ZIP (7 KB) - PSpice Model
Package Pins Download
SO (NS) 14 View options
SOIC (D) 14 View options
TSSOP (PW) 14 View options
TVSOP (DGV) 14 View options

Ordering & quality

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  • Ongoing reliability monitoring

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