The LV126A quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.
These quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.
The LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
|Part number||Order||Technology Family||VCC (Min) (V)||VCC (Max) (V)||Channels (#)||IOL (Max) (mA)||IOH (Max) (mA)||ICC (uA)||Input type||Output type||Features||Data rate (Mbps)||Rating||Operating temperature range (C)||Package Group|
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs
-40 to 125
-40 to 85
SOIC | 14
SO | 14
SSOP | 14
TSSOP | 14
TVSOP | 14