SN74LV126A Quadruple bus buffer gates with 3-state outputs | TI.com

SN74LV126A (ACTIVE) Quadruple bus buffer gates with 3-state outputs

 

Description

The ’LV126A quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.

These quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.

The ’LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

Features

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 6.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at
    VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2.3 V at
    VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial Power Down
    Mode, and Back Drive Protection
  • Support Mixed-Mode Voltage Operation on All
    Ports
  • Latch-Up Performance Exceeds 250 mA per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) IOL (Max) (mA) IOH (Max) (mA) ICC (uA) Input type Output type Features Data rate (Mbps) Rating Operating temperature range (C) Package Group
SN74LV126A Order now LV-A     2     5.5     4     16     -16     20     Standard CMOS     3-State     Balanced outputs
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
220     Catalog     -40 to 125
-40 to 85    
SOIC | 14
SO | 14
SSOP | 14
TSSOP | 14
TVSOP | 14