Product details

Technology Family LV1T Applications GPIO Bits (#) 1 Configuration 1 Ch A to B; 0 Ch B to A Vout (Min) (V) 1.65 Vout (Max) (V) 5.5 IOH (Max) (mA) -8 IOL (Max) (mA) 8 Rating Catalog
Technology Family LV1T Applications GPIO Bits (#) 1 Configuration 1 Ch A to B; 0 Ch B to A Vout (Min) (V) 1.65 Vout (Max) (V) 5.5 IOH (Max) (mA) -8 IOL (Max) (mA) 8 Rating Catalog
SOT-23 (DBV) 5 5 mm² 2.9 x 1.6 SOT-SC70 (DCK) 5 4 mm² 2 x 2.1
  • Latch-Up Performance Exceeds 250 mAPer JESD 17
  • Single-supply voltage translator at 5-V, 3.3-V, 2.5-V, and 1.8-V VCC
  • Operating range of 1.65 V to 5.5 V
  • Up translation:
    • 1.2 V(1) to 1.8 V at 1.8-V VCC
    • 1.5 V(1) to 2.5 V at 2.5-V VCC
    • 1.8 V(1) to 3.3 V at 3.3-V VCC
    • 3.3 V to 5.0 V at 5.0-V VCC
  • Down translation:
    • 3.3 V to 1.8 V at 1.8-V VCC
    • 3.3 V to 2.5 V at 2.5-V VCC
    • 5.0 V to 3.3 V at 3.3-V VCC
  • Logic output is referenced to VCC
  • Output drive:
    • 8 mA output drive at 5 V
    • 7 mA output drive at 3.3 V
    • 3 mA output drive at 1.8 V
  • Characterized up to 50 MHz at 3.3-V VCC
  • 5V Tolerance on input pins
  • –40°C to 125°C operating temperature range
  • Supports standard logic pinouts
  • CMOS output B compatible with AUP1G and LVC1G families (1)

(1)Refer to the VIH/VIL and output drive for lower VCC condition.

  • Latch-Up Performance Exceeds 250 mAPer JESD 17
  • Single-supply voltage translator at 5-V, 3.3-V, 2.5-V, and 1.8-V VCC
  • Operating range of 1.65 V to 5.5 V
  • Up translation:
    • 1.2 V(1) to 1.8 V at 1.8-V VCC
    • 1.5 V(1) to 2.5 V at 2.5-V VCC
    • 1.8 V(1) to 3.3 V at 3.3-V VCC
    • 3.3 V to 5.0 V at 5.0-V VCC
  • Down translation:
    • 3.3 V to 1.8 V at 1.8-V VCC
    • 3.3 V to 2.5 V at 2.5-V VCC
    • 5.0 V to 3.3 V at 3.3-V VCC
  • Logic output is referenced to VCC
  • Output drive:
    • 8 mA output drive at 5 V
    • 7 mA output drive at 3.3 V
    • 3 mA output drive at 1.8 V
  • Characterized up to 50 MHz at 3.3-V VCC
  • 5V Tolerance on input pins
  • –40°C to 125°C operating temperature range
  • Supports standard logic pinouts
  • CMOS output B compatible with AUP1G and LVC1G families (1)

(1)Refer to the VIH/VIL and output drive for lower VCC condition.

The SN74LV1T34 is a single buffer gate with reduced input thresholds to support voltage translation applications.

The SN74LV1T34 is a single buffer gate with reduced input thresholds to support voltage translation applications.

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Technical documentation

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Type Title Date
* Data sheet SN74LV1T34 Single Power Supply Single Buffer GATE CMOS Logic Level Shifter datasheet (Rev. C) PDF | HTML 09 Jun 2022
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 30 Apr 2015
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic EVM supporting 5 through 8 pin DCK, DCT, DCU, DRL, and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Not available on TI.com
Simulation model

SN74LV1T34 Behavioral SPICE Model

SCLM180.ZIP (7 KB) - PSpice Model
Simulation model

SN74LV1T34 IBIS Model

SCLM119.ZIP (49 KB) - IBIS Model
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Package Pins Download
SC70 (DCK) 5 View options
SOT-23 (DBV) 5 View options

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