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SN74LV540A

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8-ch, 2-V to 5.5-V inverters with 3-state outputs

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Data sheet
8-ch, 2-V to 5.5-V inverters with 3-state outputs

SN74LV540A

ACTIVE
Data sheet Order now

Product details

Technology Family LV-A Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Number of channels (#) 8 IOL (Max) (mA) 16 IOH (Max) (mA) -16 ICC (Max) (uA) 20 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Rating Catalog
Technology Family LV-A Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Number of channels (#) 8 IOL (Max) (mA) 16 IOH (Max) (mA) -16 ICC (Max) (uA) 20 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Rating Catalog
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SOIC (DW) 20 132 mm² 12.8 x 10.3 SOP (NS) 20 98 mm² 12.6 x 7.8 SSOP (DB) 20 38 mm² 5.3 x 7.2 TSSOP (PW) 20 42 mm² 6.5 x 6.4 TVSOP (DGV) 20 32 mm² 5 x 6.4 VQFN (RGY) 20 16 mm² 3.5 x 4.5
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  • 2-V to 5.5-V VCC Operation
  • Max tpd of 8.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Ioff Supports Partial-Power-Down Mode
    Operation
  • Latch-Up Performance Exceeds 250 mA
    Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 200-V Machine Model
    • 2000-V Charged-Device Model
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 8.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Ioff Supports Partial-Power-Down Mode
    Operation
  • Latch-Up Performance Exceeds 250 mA
    Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 200-V Machine Model
    • 2000-V Charged-Device Model
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The SN74LV540A device is an octal buffer/driver designed for 2-V to 5.5-V VCC operation.

This device is ideal for driving bus lines or buffer memory address registers. It features inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.

The SN74LV540A device is an octal buffer/driver designed for 2-V to 5.5-V VCC operation.

This device is ideal for driving bus lines or buffer memory address registers. It features inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.

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Technical documentation

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Type Title Date
* Data sheet SN74LV540A Octal Buffers/Drivers with 3-State Outputs datasheet (Rev. I) 27 Dec 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, P, N, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
document-pdfAcrobat User guide
In stock
Limit: 5
Evaluation board

14-24-NL-LOGIC-EVM — Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
document-pdfAcrobat User guide
In stock
Limit: 10
Simulation model

SN74LV540A IBIS Model

SCEM143.ZIP (18 KB) - IBIS Model
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Simulation model

SN74LV540A Behavioral SPICE Model

SCLM178.ZIP (7 KB) - PSpice Model
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Package Pins Download
SO (NS) 20 View options
SOIC (DW) 20 View options
SSOP (DB) 20 View options
TSSOP (PW) 20 View options
TVSOP (DGV) 20 View options
VQFN (RGY) 20 View options

Ordering & quality

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  • Qualification summary
  • Ongoing reliability monitoring

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