SN74LVC06A-Q1

ACTIVE

Automotive Catalog Hex Inverter Buffers/Drivers With Open-Drain Outputs

Top
Automotive Catalog Hex Inverter Buffers/Drivers With Open-Drain Outputs

SN74LVC06A-Q1

ACTIVE

Product details

Parameters

Technology Family LVC VCC (Min) (V) 1.65 VCC (Max) (V) 3.6 Channels (#) 6 IOL (Max) (mA) 24 IOH (Max) (mA) 0 ICC (Max) (uA) 10 Input type Standard CMOS Output type Open-Drain Features Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Data rate (Mbps) 200 Rating Automotive open-in-new Find other Inverting buffer/driver

Package | Pins | Size

SOIC (D) 14 52 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other Inverting buffer/driver

Features

  • Qualified for Automotive Applications
  • Operate From 1.65 V to 3.6 V
  • Inputs and Open-Drain Outputs Accept Voltages up to 5.5 V
  • Max tpd of 3.7 ns at 3.3 V
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17

open-in-new Find other Inverting buffer/driver

Description

This hex inverter buffer/driver is designed for 1.65-V to 3.6-V VCC operation.

The outputs of the SN74LVC06A device are open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 24 mA.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

open-in-new Find other Inverting buffer/driver
Download

Technical documentation

= Featured
No results found. Please clear your search and try again. View all 30
Type Title Date
* Datasheet Hex Inverter Buffer/Driver With Open-Drain Outputs datasheet (Rev. B) Apr. 09, 2008
Selection guides Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes How to Select Little Logic (Rev. A) Jul. 26, 2016
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
More literature Automotive Logic Devices Brochure Aug. 27, 2014
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
Application notes Use of the CMOS Unbuffered Inverter in Oscillator Circuits Nov. 06, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
User guides LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) Dec. 18, 2002
Application notes Texas Instruments Little Logic Application Report Nov. 01, 2002
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application notes 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application notes Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS Mar. 27, 2002
More literature Military Low Voltage Solutions Apr. 04, 2001
Application notes Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes LVC Characterization Information Dec. 01, 1996
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
User guides Low-Voltage Logic (LVC) Designer's Guide Sep. 01, 1996
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCAM115.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
SOIC (D) 14 View options
TSSOP (PW) 14 View options

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos

Related videos