SN74LVC126A Quadruple Bus Buffer Gate With 3-State Outputs | TI.com

SN74LVC126A (ACTIVE) Quadruple Bus Buffer Gate With 3-State Outputs

 

Description

The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65-V to 3.6-V VCC operation.

The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V and 5-V system environment.

Features

  • Operates From 1.65 V to 3.6 V
  • Specified From –40°C to +125°C
  • Inputs Accept Voltages up to 5.5 V
  • Maximum tpd of 4.7 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce), <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot), >2 V at VCC = 3.3 V, TA = 25°C
  • Latch-Up Performance Exceeds 250 mA Per JESD 17

Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) IOL (Max) (mA) IOH (Max) (mA) ICC (uA) Input type Output type Features Data rate (Mbps) Rating Operating temperature range (C) Package Group
SN74LVC126A Order now LVC     1.65     3.6     4     24     -24     40     Standard CMOS     3-State     Balanced outputs
Very high speed (tpd 5-10ns)
Over-voltage tolerant inputs    
200     Catalog     -40 to 125     SOIC | 14
SO | 14
SSOP | 14
TSSOP | 14
TVSOP | 14
VQFN | 14    
SN74LVC126A-Q1 Samples not available LVC     1.65     3.6     4     24     -24     20     Standard CMOS     3-State     Balanced outputs
Very high speed (tpd 5-10ns)
Over-voltage tolerant inputs    
200     Automotive     -40 to 125     SOIC | 14
TSSOP | 14