SN74LVC1G125 Single Bus Buffer Gate With 3-State Outputs

Description

This bus buffer gate is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC1G125 device is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.

The CMOS device has high output drive while maintaining low static power dissipation over a broad V_CC operating range.

The SN74LVC1G125 device is available in a variety of packages including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.

Available in the Ultra Small 0.64-mm²
Package (DPW) With 0.5-mm Pitch
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Provides Down Translation to V_CC
Max t_pd of 3.7 ns at 3.3 V
Low Power Consumption, 10-μA Max I_CC
±24-mA Output Drive at 3.3 V
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

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Part number	Order	Technology Family	VCC (Min) (V)	VCC (Max) (V)	Channels (#)	IOL (Max) (mA)	IOH (Max) (mA)	ICC (uA)	Input type	Output type	Features	Data rate (Mbps)	Rating	Operating temperature range (C)	Package Group
SN74LVC1G125	Order now	LVC	1.65	5.5	1	32	-32	10	Standard CMOS	3-State	Balanced outputs Very high speed (tpd 5-10ns) Partial power down (Ioff) Over-voltage tolerant inputs	300	Catalog	-40 to 125 -40 to 85	DSBGA \| 5 SC70 \| 5 SON \| 6 SOT-23 \| 5 SOT-5X3 \| 5 X2SON \| 5
SN74LVC1G125-EP	Samples not available	LVC	1.65	5.5	1	32	-32	10	Standard CMOS	3-State	Balanced outputs Very high speed (tpd 5-10ns) Partial power down (Ioff) Over-voltage tolerant inputs	300	HiRel Enhanced Product	-40 to 85 -55 to 125	SC70 \| 5