Home Logic & voltage translation Buffers, drivers & transceivers Noninverting buffers & drivers
Home
Logic & voltage translation
Buffers, drivers & transceivers
Noninverting buffers & drivers

SN74LVC1G125

ACTIVE

Single 1.65-V to 5.5-V buffer with 3-state outputs

Order now
Data sheet
Single 1.65-V to 5.5-V buffer with 3-state outputs

SN74LVC1G125

ACTIVE
Data sheet Order now

Product details

Technology Family LVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 5.5 Number of channels (#) 1 IOL (Max) (mA) 32 ICC (Max) (uA) 10 IOH (Max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Rating Catalog
Technology Family LVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 5.5 Number of channels (#) 1 IOL (Max) (mA) 32 ICC (Max) (uA) 10 IOH (Max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Rating Catalog
open-in-new Find other Noninverting buffers & drivers
DSBGA (YZP) 5 2 mm² .928 x 1.428 SOT-23 (DBV) 5 5 mm² 2.9 x 1.6 SOT-5X3 (DRL) 5 2 mm² 1.65 x 1.2 SOT-SC70 (DCK) 5 4 mm² 2 x 2.1 USON (DRY) 6 1 mm² 1.5 x 1 X2SON (DPW) 5 1 mm² .8 x .8 X2SON (DSF) 6 1 mm² 1 x 1
open-in-new Find other Noninverting buffers & drivers
  • Available in the Ultra Small 0.64-mm2
    Package (DPW) With 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 3.7 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Ultra Small 0.64-mm2
    Package (DPW) With 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 3.7 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
open-in-new Find other Noninverting buffers & drivers

This bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G125 device is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G125 device is available in a variety of packages including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.

This bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G125 device is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G125 device is available in a variety of packages including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.

open-in-new Find other Noninverting buffers & drivers
Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 30
Type Title Date
* Data sheet SN74LVC1G125 Single Bus Buffer Gate With 3-State Output datasheet (Rev. T) 21 Oct 2014
Application note Enabling Optimal Solar Inverter Power Stage Designs with Logic 17 Aug 2021
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Application note Designing and Manufacturing with TI's X2SON Packages 23 Aug 2017
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic EVM supporting 5 through 8 pin DCK, DCT, DCU, DRL, and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
document-pdfAcrobat User guide
In stock
Limit: 5
Simulation model

HSPICE Model for SN74LVC1G125

SCEJ253.ZIP (87 KB) - HSpice Model
Download
Simulation model

SN74LVC1G125 IBIS Model (Rev. B)

SCEM270B.ZIP (53 KB) - IBIS Model
Download
Simulation model

SN74LVC1G125 PSpice Model

SCEM579.ZIP (20 KB) - PSpice Model
Download
Simulation model

SN74LVC1G125 Behavioral SPICE Model

SCEM639.ZIP (7 KB) - PSpice Model
Download
Many TI reference designs include the SN74LVC1G125

Use our reference design selection tool to review and identify designs that best match your application and parameters.
View reference designs
Package Pins Download
DSBGA (YZP) 5 View options
SC70 (DCK) 5 View options
SON (DRY) 6 View options
SON (DSF) 6 View options
SOT-23 (DBV) 5 View options
SOT-5X3 (DRL) 5 View options
X2SON (DPW) 5 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos