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Product details

Parameters

Technology Family LVC VCC (Min) (V) 1.65 VCC (Max) (V) 5.5 Channels (#) 2 Inputs per channel 2 IOL (Max) (mA) 32 IOH (Max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Partial Power Down (Ioff), Over-Voltage Tolerant Inputs, Ultra High Speed (tpd <5ns) Data rate (Max) (Mbps) 100 Rating Catalog Operating temperature range (C) -40 to 125 open-in-new Find other NAND gate

Package | Pins | Size

DSBGA (YZP) 8 3 mm² .927 x 1.928 SSOP (DCT) 8 12 mm² 2.95 x 4 VSSOP (DCU) 8 6 mm² 2 x 3.1 open-in-new Find other NAND gate

Features

  • Available in the Texas Instruments
    NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA =
    25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial Power
    Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 1000-V Charged-Device Model
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Description

This dual 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G00 device performs the Boolean function Y = A × B or Y = A + B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

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Type Title Date
* Datasheet SN74LVC2G00 Dual 2-Input Positive-NAND Gate datasheet (Rev. N) Jan. 12, 2015
Selection guides Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes How to Select Little Logic (Rev. A) Jul. 26, 2016
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Solution guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
Application notes Use of the CMOS Unbuffered Inverter in Oscillator Circuits Nov. 06, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
User guides LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) Dec. 18, 2002
Application notes Texas Instruments Little Logic Application Report Nov. 01, 2002
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application notes 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application notes Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS Mar. 27, 2002
More literature Military Low Voltage Solutions Apr. 04, 2001
Application notes Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes LVC Characterization Information Dec. 01, 1996
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
User guides Low-Voltage Logic (LVC) Designer's Guide Sep. 01, 1996
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCEM251A.ZIP (45 KB) - IBIS Model
SIMULATION MODELS Download
SCEM625.ZIP (7 KB) - PSpice Model

Reference designs

REFERENCE DESIGNS Download
Camera Reference Design for ARM® Cortex®-M Microcontrollers (MCUs)
TIDM-TM4C129CAMERA This design implements a network camera with a QVGA display panel and an embedded web server for remote monitoring.  With a memory footrpint of 250KB for the web server, there is ample memory available on the TM4C129x microcontroller for additional customizations.
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Hardware Pace Detection for ECG Reference Design
TIPD111 This Verified Design outlines a hardware pace detection solution for ECG using slope detection. The circuit is designed to work smoothly with the ADS1298 through the PACEOUT pins from the ADC directly feeding the input of the pace detection circuit. When a pace signal is detected, the output from (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
DSBGA (YZP) 8 View options
SM8 (DCT) 8 View options
VSSOP (DCU) 8 View options

Ordering & quality

Support & training

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