SN74LVC2T45

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DSBGA (YZP)

8

3 mm² .928 x 1.928

SSOP (DCT)

8

8 mm² 2.95 x 2.80

SSOP (DCT)

8

8 mm² 3 x 2.8

VSSOP (DCU)

8

6 mm² 2 x 3.1

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Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
V_CC Isolation Feature – If Either V_CCInput Is at GND, Both Ports Are in the High-Impedance State
DIR Input Circuit Referenced to V_CCA
Low Power Consumption, 4-µA Max I_CC
Available in the Texas Instruments NanoFree™ Package
±24-mA Output Drive at 3.3 V
I_off Supports Partial-Power-Down Mode Operation
Max Data Rates
- 420 Mbps (3.3-V to 5-V Translation)
- 210 Mbps (Translate to 3.3 V)
- 140 Mbps (Translate to 2.5 V)
- 75 Mbps (Translate to 1.8 V)
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 4000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
V_CC Isolation Feature – If Either V_CCInput Is at GND, Both Ports Are in the High-Impedance State
DIR Input Circuit Referenced to V_CCA
Low Power Consumption, 4-µA Max I_CC
Available in the Texas Instruments NanoFree™ Package
±24-mA Output Drive at 3.3 V
I_off Supports Partial-Power-Down Mode Operation
Max Data Rates
- 420 Mbps (3.3-V to 5-V Translation)
- 210 Mbps (Translate to 3.3 V)
- 140 Mbps (Translate to 2.5 V)
- 75 Mbps (Translate to 1.8 V)
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 4000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

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This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track V_CCA. V_CCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track V_CCB. V_CCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess I_CC and I_CCZ.

The SN74LVC2T45 is designed so that the DIR input circuit is supplied by V_CCA. This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The V_CC isolation feature ensures that if either V_CC input is at GND, both ports are in the high-impedance state. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track V_CCA. V_CCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track V_CCB. V_CCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess I_CC and I_CCZ.

The SN74LVC2T45 is designed so that the DIR input circuit is supplied by V_CCA. This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The V_CC isolation feature ensures that if either V_CC input is at GND, both ports are in the high-impedance state. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

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Technical documentation

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	Type	Title	Date
*	Data sheet	SN74LVC2T45 Dual-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation datasheet (Rev. K)	15 May 2017
	User guide	Generic AVC and LVC Direction Controlled Translation EVM (Rev. B)	30 Jul 2021
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 Jul 2021
	Selection guide	Voltage Translation Buying Guide (Rev. A)	15 Apr 2021
	Selection guide	Little Logic Guide 2018 (Rev. G)	06 Jul 2018
	Selection guide	Logic Guide (Rev. AB)	12 Jun 2017
	Application note	How to Select Little Logic (Rev. A)	26 Jul 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 Dec 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 Jan 2007
	More literature	Design Summary for WCSP Little Logic (Rev. B)	04 Nov 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	22 Jun 2004
	User guide	Signal Switch Data Book (Rev. A)	14 Nov 2003
	Application note	Use of the CMOS Unbuffered Inverter in Oscillator Circuits	06 Nov 2003
	More literature	Logic Cross-Reference (Rev. A)	07 Oct 2003
	User guide	LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)	18 Dec 2002
	Application note	Texas Instruments Little Logic Application Report	01 Nov 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 Aug 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards	13 Jun 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)	22 May 2002
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices	10 May 2002
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS	27 Mar 2002
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices	01 Dec 1997
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	01 Aug 1997
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	01 Jun 1997
	Application note	LVC Characterization Information	01 Dec 1996
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 Oct 1996
	Application note	Live Insertion	01 Oct 1996
	Design guide	Low-Voltage Logic (LVC) Designer's Guide	01 Sep 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide	01 May 1996

Design & development

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Evaluation board

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Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.

User guide

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Evaluation board

AVCLVCDIRCNTRL-EVM — Generic EVM for Direction-Controlled Bidirectional Translation Device Supporting AVC and LVC

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC is (...)

User guide

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Simulation model

SN74LVC2T45 IBIS Model (Rev. A)

SCEM409A.ZIP (95 KB) - IBIS Model

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