THS6072

ACTIVE

Product details

Number of channels (#) 2 Architecture DSL Line Driver Total supply voltage (Min) (+5V=5, +/-5V=10) 9 Total supply voltage (Max) (+5V=5, +/-5V=10) 32 BW @ Acl (MHz) 175 Acl, min spec gain (V/V) 1 Vn at flatband (Typ) (nV/rtHz) 10 Vn at 1 kHz (Typ) (nV/rtHz) 13 Iq per channel (Typ) (mA) 3.4 Vos (offset voltage @ 25 C) (Max) (mV) 7 Rail-to-rail No Features Operating temperature range (C) -40 to 85, 0 to 70 CMRR (Typ) (dB) 90 Input bias current (Max) (pA) 10000000 Offset drift (Typ) (uV/C) 15 GBW (Typ) (MHz) 175 Output current (Typ) (mA) 85 2nd harmonic (dBc) 81 3rd harmonic (dBc) 87 @ MHz 1
Number of channels (#) 2 Architecture DSL Line Driver Total supply voltage (Min) (+5V=5, +/-5V=10) 9 Total supply voltage (Max) (+5V=5, +/-5V=10) 32 BW @ Acl (MHz) 175 Acl, min spec gain (V/V) 1 Vn at flatband (Typ) (nV/rtHz) 10 Vn at 1 kHz (Typ) (nV/rtHz) 13 Iq per channel (Typ) (mA) 3.4 Vos (offset voltage @ 25 C) (Max) (mV) 7 Rail-to-rail No Features Operating temperature range (C) -40 to 85, 0 to 70 CMRR (Typ) (dB) 90 Input bias current (Max) (pA) 10000000 Offset drift (Typ) (uV/C) 15 GBW (Typ) (MHz) 175 Output current (Typ) (mA) 85 2nd harmonic (dBc) 81 3rd harmonic (dBc) 87 @ MHz 1
HVSSOP (DGN) 8 9 mm² 3 x 3 SOIC (D) 8 19 mm² 3.91 x 4.9
Download

Technical documentation

No results found. Please clear your search and try again.
View all 4
Type Title Date
E-book The Signal e-book: A compendium of blog posts on op amp design topics 28 Mar 2017
Application note Noise Analysis for High Speed Op Amps (Rev. A) 17 Jan 2005
Application note Active Output Impedance for ADSL Line Drivers 26 Nov 2002
User guide THS6072 Dual High-Speed Operational Amplifier Evaluation Module 07 Sep 2000

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

THS6072 TINA-TI Reference Design (Rev. B)

SLAC109B.TSC (98 KB) - TINA-TI Reference Design
Simulation model

THS6072 TINA-TI Spice Model (Rev. B)

SLAM038B.ZIP (4 KB) - TINA-TI Spice Model
Simulation model

THS6072 PSpice Model (Rev. B)

SLOJ030B.ZIP (97 KB) - PSpice Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Package Pins Download
HVSSOP (DGN) 8 View options
SOIC (D) 8 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos