Packaging information
| Package | Pins LQFP (PZ) | 100 |
| Operating temperature range (°C) |
| Package qty | Carrier 90 | JEDEC TRAY (5+1) |
Features for the TMS320LC206
- High-Performance Static CMOS Technology
- Includes the '320C2xLP Core CPU
- TMS320C206, TMS320LC206 are Members of the 'C20x/'C2000 Platform Which Also Includes the TMS320C203/LC203 and TMS320F206 Devices
- Instruction-Cycle Time 25 ns at 3.3 V
- Source Code Compatible With TMS320C25 and other '20x Devices
- Upwardly Code-Compatible With TMS320C5x Devices
- Four External Interrupts
- TMS320C206, 5-V I/O (3.3-V core)
- TMS320LC206, 3.3-V core and I/O
- TMS320C206, TMS320LC206 Integrated Memory:
- 544 × 16 Words of On-Chip Dual-Access Data RAM
- 32K × 16 Words of On-Chip ROM
- 4K × 16 Words of On-Chip Single-Access Program/Data RAM
- 224K × 16-Bit Maximum Addressable External Memory Space
- 64K Program
- 64K Data
- 64K Input/Output (I/O)
- 32K Global
- 32-Bit Arithmetic Logic Unit (ALU) Accumulator
- 16 × 16-Bit Multiplier With a 32-Bit Product
- Block Moves from Data and Program Space
- TMS320C206, TMS320LC206 Peripherals:
- On-Chip 20-Bit Timer
- On-Chip Software-Programmable Wait-State (0 to 7) Generator
- On-Chip Oscillator
- On-Chip Phase-Locked Loop (PLL)
- Six General-Purpose I/O Pins
- Full-Duplex Asynchronous Serial Port (UART)
- Enhanced Synchronous Serial Port (ESSP) With Four-Level-Deep FIFOs
- Input Clock Options
- Options: Multiply-by-One, -Two, or -Four, and Divide-by-Two (1, 2, 4, and 2)
- Support of Hardware Wait States
- Power Down IDLE Mode
- IEEE 1149.1
-Compatible Scan-Based Emulation - TMS320C206, TMS320LC206 100-Pin PZ Package, Small Thin Quad Flat Package (TQFP)
- Industrial Temperature Version Planned,
(- 40°C to 85°C) IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port
Device numbers are hereafter referred to in the data sheet as 'C206, unless otherwise specified.
TI is a trademark of Texas Instruments Incorporated.
Description for the TMS320LC206
The Texas Instruments (TITM) TMS320C206 digital signal processors (DSPs) are fabricated with static CMOS integrated-circuit technology. The architectural design is based upon that of the TMS320C20x series and is optimized for low-power operation. The combination of advanced Harvard architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of the 'C206.
The 'C206 offers these advantages:
- Enhanced TMS320 architectural design for increased performance and versatility
- Advanced integrated-circuit processing technology for increased performance
- 'C206 devices are pin- and code-compatible with 'C203 and 'F206 devices.
- Source code for the 'C206 DSPs is software-compatible with the 'C1x and 'C2x DSPs and is upwardly compatible with fifth-generation DSPs ('C5x)
- New static-design techniques for minimizing power consumption and increasing radiation tolerance