Synchronous buck FET driver for high-frequency CPU core power in automotive applications
Product details
Parameters
Package | Pins | Size
Features
- AEC-Q100 Qualified for Automotive Applications
- Device Temperature Grade 1: –40°C to 125°C
- Device Human Body Model ESD Classification Level H2
- Device Charged Device Model ESD Classification Level C3B
- Reduced Dead-Time Drive Circuit for Optimized CCM
- Automatic Zero Crossing Detection for Optimized DCM Efficiency
- Multiple Low-Power Modes for Optimized Light-Load Efficiency
- Optimized Signal Path Delays for High-Frequency Operation
- Integrated BST Switch Drive Strength Optimized for low RdsON FETs
- Optimized for 5-V FET Drive
- Conversion Input Voltage Range (VIN): 2.5 to 28 V
- 2-mm × 2-mm, 8-Pin, WSON Thermal Pad Package with wettable flanks
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Description
The TPS59603-Q1 drivers are optimized for high-frequency CPU VCORE applications. Advanced features such as reduced dead-time drive and auto zero crossing are used to optimize efficiency over the entire load range.
The SKIP pin provides the option of CCM operation to support controlled management of the output voltage. In addition, the TPS59603-Q1 supports two low-power modes. With the PWM input in tri-state, quiescent current is reduced to 130 µA, with immediate response. When SKIP is held at tri-state, the current is reduced to 8 µA (typically 20 µs is required to resume switching). Paired with the appropriate TI controller, the drivers deliver an exceptionally high performance power supply system.
The TPS59603-Q1 device is packaged in a space saving, thermally-enhanced 8-pin, 2-mm x 2-mm wettable flanks WSON package and operates from –40°C to 125°C.
Technical documentation
Design & development
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Description
Features
- Configurable to 1, 2 or 3 phase
- Automotive qualified controller and driver
- Each phase can deliver maximum transient current up to 20A and continuous current up to 15A
- On-board Transient Load Generator
- I²C port for external communication
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
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CAD/CAE symbols
Package | Pins | Download |
---|---|---|
WSON (DSG) | 8 | View options |
Ordering & quality
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- MTBF/FIT estimates
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- Qualification summary
- Ongoing reliability monitoring
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