3.3-V, 2:1 (SPDT), 12-channel switch for DDR3 applications


Product details


Protocols DDR3 Configuration 2:1 SPDT Number of channels (#) 12 Bandwidth (MHz) 1675 Supply voltage (Max) (V) 3.6 Supply voltage (Min) (V) 3 Ron (Typ) (Ohms) 8 Input/ouput voltage (Min) (V) 0 Input/ouput voltage (Max) (V) 3.6 Supply current (Typ) (uA) 300 ESD HBM (Typ) (kV) 2 Operating temperature range (C) -40 to 85 Crosstalk (dB) -71 ESD CDM (kV) 1 ICC (Typ) (uA) 300 Input/output continuous current (Max) (mA) 128 COFF (Typ) (pF) 5.6 CON (Typ) (pF) 2 Off isolation (Typ) (dB) -42 OFF-state leakage current (Max) (µA) 1 Propagation delay (ns) 0.04 Ron (Max) (Ohms) 12 Ron channel match (Max) (Ohms) 1 RON flatness (Typ) (Ohms) 1.5 Turn off time (disable) (Max) (ns) 5 Turn on time (enable) (Max) (ns) 7 VIH (Min) (V) 2 VIL (Max) (V) 0.8 open-in-new Find other Protocol-specific switches & muxes

Package | Pins | Size

WQFN (RUA) 42 32 mm² 9 x 3.5 open-in-new Find other Protocol-specific switches & muxes


  • Compatible with DDR3 SDRAM Standard (JESD79-3D)
  • Wide Bandwidth of 1.675 GHz
  • Low Propagation Delay (tpd = 40 ps Typ)
  • Low Bit-to-Bit Skew (tsk(o) = 6 ps Typ)
  • Low and Flat ON-State Resistance
    (rON = 8 Ω Typ)
  • Low Input/Output Capacitance
    (CON = 5.6 pF Typ)
  • Low Crosstalk (XTALK = –43 dB,
    Typ at 250 MHz)
  • VCC Operating Range from 3 V to 3.6 V
  • Rail-to-Rail Switching on Data I/O Ports
    (0 to VCC)
  • Separate Switch Control Logic for Upper and Lower 6-Channels
  • Dedicated Enable Logic Supports Hi-Z Mode
  • IOFF Protection Prevents Current Leakage in Powered Down State (VCC = 0 V)
  • ESD Performance Tested Per JESD22
    • 2000 V Human Body Model
      (A114B, Class II)
    • 1000 V Charged Device Model (C101)
  • 42-pin RUA Package (9 × 3.5 mm, 0.5 mm Pitch)
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The TS3DDR3812 is a 12-channel, 1:2 multiplexer/demultiplexer switch designed for DDR3 applications. It operates from a 3 to 3.6 V supply and offers low and flat ON-state resistance as well as low I/O capacitance which allow it to achieve a typical bandwidth of 1.675 GHz.

Channels A0 through A11 are divided into two banks of six bits and are independently controlled via two digital inputs called SEL1 and SEL2. These select inputs control the switch position of each 6-bit DDR3 source and allow them to be routed to one of two end-points. Alternatively, the switch can be used to connect a single endpoint to one of two 6-bit DDR3 sources. For switching 12-bit DDR3 sources, simply connect SEL1 and SEL2 together externally and control all 12 channels with a single GPIO input. An EN input allows the entire chip to be placed into a high-impedance (Hi-Z) state while not in use.

These characteristics make the TS3DDR3812 an excellent choice for use in memory, analog/digital video, LAN, and other high-speed signal switching applications.

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Exact equivalent in functionality and parametrics to the compared device:
TS3DDR4000 ACTIVE 3.3-V, 2:1 (SPDT), 12-channel DDR2, DDR3 & DDR4 switch Flipped logic polarity (normally closed)

Technical documentation

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No results found. Please clear your search and try again. View all 4
Type Title Date
* Datasheet 12-CHANNEL, 1:2 MUX/DEMUX SWITCH FOR DDR3 APPLICATIONS datasheet (Rev. B) Jun. 03, 2013
Technical articles Roll with the design punches and overcome power-sequencing challenges Jul. 29, 2019
Application notes Preventing Excess Power Consumption on Analog Switches Jul. 03, 2008
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004

Design & development

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Design tools & simulation

SCDM134.ZIP (113 KB) - HSpice Model
SCDM135.ZIP (24 KB) - IBIS Model

CAD/CAE symbols

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WQFN (RUA) 42 View options

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