UCC28500

ACTIVE

PFC/PWM Combination controller with 16V/10V VCC UVLO and 6.75V/5.5V)PWM UVLO,-40°C to 85°C

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Product details

Parameters

Device type PFC+PWM Control method CCM Operating supply (Max) (V) 18 Operating supply current (mA) 4 UVLO thresholds on/off (V) 16/10 Features Average Current Mode, Enable, OVP Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Power factor correction (PFC) controllers

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 open-in-new Find other Power factor correction (PFC) controllers

Features

  • Combines PFC and Downstream Converter Controls
  • Controls Boost Preregulator to Near-Unity Power Factor
  • Accurate Power Limiting
  • Improved Feedforward Line Regulation
  • Peak Current-Mode Control in Second Stage
  • Programmable Oscillator
  • Leading-Edge/Trailing-Edge Modulation for Reduced Output Ripple
  • Low Start-up Supply Current
  • Synchronized Second Stage Start-Up, with Programmable Soft-start
  • Programmable Second Stage Shutdown

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Description

The UCC2850x family provides all of the control functions necessary for an active power-factor-corrected preregulator and a second-stage dc-to-dc converter. The controller achieves near-unity power factor by shaping the ac input line current waveform to correspond to the ac input-line voltage using average current-mode control. The dc-to-dc converter uses peak current-mode control to perform the step-down power conversion.

The PFC stage is leading-edge modulated while the second stage is trailing-edge synchronized to allow for minimum overlap between the boost and PWM switches. This reduces ripple current in the bulk-output capacitor.In order to operate with over three-to-one range of input-line voltages, a line feedforward (VFF) is used to keep input power constant with varying input voltage. Generation of VFF is accomplished using IAC in conjunction with an external single-pole filter. This not only reduces external parts count, but also avoids the use of high-voltage components, offering a lower-cost solution. The multiplier then divides the line current by the square of VFF.

The UCC2850x PFC section incorporates a low offset-voltage amplifier with 7.5-V reference, a highly-linear multiplier capable of a wide current range, a high-bandwidth, low offset-current amplifier, with a novel noise-attenuation configuration, PWM comparator and latch, and a high-current output driver. Additional PFC features include over-voltage protection, zero-power detection to turn off the output when VAOUT is below 0.33 V and peak current and power limiting.

The dc-to-dc section relies on an error signal generated on the secondary-side and processes it by performing peak current mode control. The dc-to-dc section also features current limiting, a controlled soft-start, preset operating range with selectable options, and 50% maximum duty cycle.

The UCC28500 and UCC28502 have a wide PFC-UVLO threshold (16.5 V/10 V) for bootstrap bias supply operation. The UCC28501 and UCC28503 are designed with a narrow UVLO range (10.5 V/10 V) more suitable for fixed bias operation. The UCC28500 and UCC28501 have a narrow UVLO threshold for PWM stage (to allow operation down to 75% of nominal bulk voltage), while the UCC28502 and UCC38503 are configured for a much wider operation range for the PWM stage (down to 50% of bulk nominal voltage).

Available in 20-pin N and DW packages.

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Technical documentation

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Type Title Date
* Datasheet BiCMOS PFC/PWM Combination Controller datasheet (Rev. C) Nov. 08, 2001
Application notes Avoiding Audible Noise at Light Loads When Using Leading Edge Triggered PFC Con (Rev. C) Apr. 13, 2011
Application notes A New Synchronization Circuit for Power Converters (Rev. A) Apr. 21, 2010
Application notes Bootstrap Circuit for Green Mode Applications Jan. 27, 2006
Application notes Startup Current transient of the Leading Edge Triggered PFC Controllers Jun. 30, 2004
Application notes Accurate PWM Duty Cycle Clamp Jan. 25, 2002
Application notes DN-66 UC3854A/B and UC3855A/B Provide Power Limiting with Sinusoidal Input (Rev. A) Nov. 06, 2001

Design & development

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CAD/CAE symbols

Package Pins Download
PDIP (N) 20 View options
SOIC (DW) 20 View options

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