ADS54J42

AKTIV

Zweikanaliger Analog-zu-Digital-Wandler (ADC), 14 Bit, 625 MSPS

Jetzt bestellen

Datenblatt

document-pdfAcrobat ADS54J42 Dual-Channel, 14-Bit, 625-MSPS, Analog-to-Digital Converter datasheet (Rev. A) (Englisch) PDF | HTML

ADS54J42

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Sample rate (max) (Msps)

625

Resolution (Bits)

14

Number of input channels

2

Interface type

JESD204B

Analog input BW (MHz)

1200

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

1.9

Power consumption (typ) (mW)

1940

Architecture

Pipeline

SNR (dB)

71.8

ENOB (Bits)

11.6

SFDR (dB)

93

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

Sample rate (max) (Msps)

625

Resolution (Bits)

14

Number of input channels

2

Interface type

JESD204B

Analog input BW (MHz)

1200

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

1.9

Power consumption (typ) (mW)

1940

Architecture

Pipeline

SNR (dB)

71.8

ENOB (Bits)

11.6

SFDR (dB)

93

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

VQFNP (RMP)

72

100 mm² (10 mm × 10 mm)

14-Bit Resolution, Dual-Chanel, 625-MSPS ADC
Noise Floor: –157 dBFS/Hz
Spectral Performance (f_IN = 170 MHz at –1 dBFS):
- SNR: 71.0 dBFS
- NSD: –155.9 dBFS/Hz
- SFDR: 85 dBc
- SFDR: 93 dBc (Except HD2, HD3, and Interleaving Tones)
Spectral Performance (f_IN = 350 MHz at –1 dBFS):
- SNR: 69 dBFS
- NSD: –153.9 dBFS/Hz
- SFDR: 76 dBc
- SFDR: 90 dBc (Except HD2, HD3, and Interleaving Tones)
Channel Isolation: 100 dBc at f_IN = 170 MHz
Input Full-Scale: 1.9 V_PP
Input Bandwidth (3 dB): 1.2 GHz
On-Chip Dither
Integrated Wideband DDC Block
JESD204B Interface with Subclass 1 Support:
- 2 Lanes per ADC at 6.25 Gbps
- 4 Lanes per ADC at 3.125 Gbps
- Support for Multi-Chip Synchronization
Power Dissipation: 970 mW/Ch at 625 MSPS
Package: 72-Pin VQFNP (10 mm × 10 mm)

14-Bit Resolution, Dual-Chanel, 625-MSPS ADC
Noise Floor: –157 dBFS/Hz
Spectral Performance (f_IN = 170 MHz at –1 dBFS):
- SNR: 71.0 dBFS
- NSD: –155.9 dBFS/Hz
- SFDR: 85 dBc
- SFDR: 93 dBc (Except HD2, HD3, and Interleaving Tones)
Spectral Performance (f_IN = 350 MHz at –1 dBFS):
- SNR: 69 dBFS
- NSD: –153.9 dBFS/Hz
- SFDR: 76 dBc
- SFDR: 90 dBc (Except HD2, HD3, and Interleaving Tones)
Channel Isolation: 100 dBc at f_IN = 170 MHz
Input Full-Scale: 1.9 V_PP
Input Bandwidth (3 dB): 1.2 GHz
On-Chip Dither
Integrated Wideband DDC Block
JESD204B Interface with Subclass 1 Support:
- 2 Lanes per ADC at 6.25 Gbps
- 4 Lanes per ADC at 3.125 Gbps
- Support for Multi-Chip Synchronization
Power Dissipation: 970 mW/Ch at 625 MSPS
Package: 72-Pin VQFNP (10 mm × 10 mm)

The ADS54J42 is a low-power, wide-bandwidth, 14-bit, 625-MSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –157 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 6.25 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J42 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.

The ADS54J42 is a low-power, wide-bandwidth, 14-bit, 625-MSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –157 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 6.25 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J42 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.

filter

Andere Highspeed-ADCs (≥ 10 MSPS) suchen

Herunterladen Video mit Transkript ansehen Video

Technische Dokumentation

Keine Ergebnisse gefunden. Bitte geben Sie einen anderen Begriff ein und versuchen Sie es erneut.

Alle anzeigen 1

Top-Dokumentation	Typ	Titel	Format-Optionen	Neueste englische Version herunterladen	Datum
*	Datenblatt	ADS54J42 Dual-Channel, 14-Bit, 625-MSPS, Analog-to-Digital Converter datasheet (Rev. A)	PDF \| HTML		31.03.2016

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Firmware

TI204C-IP — Request for JESD204 rapid design IP

Die JESD204 Rapid Design IP ist dazu entwickelt worden, FPGA-Technikern einen beschleunigten Weg zu einem funktionierenden JESD204-System zu ermöglichen. Diese IP ist derart ausgelegt worden, dass nachgelagerte digitale Verarbeitung und sonstige Anwendungslogik von den meisten leistungs- und (...)