Gehäuseinformationen
| Gehäuse | Pins VQFN (RGE) | 24 |
| Betriebstemperaturbereich (°C) -40 to 85 |
| Gehäusemenge | Träger 3.000 | LARGE T&R |
Merkmale von CDCI6214
- One configurable high performance, low-power PLL with four programmable outputs
- RMS jitter performance
- Supports PCIe Gen1/ Gen2 / Gen3 / Gen4 without SSC
- Typical power consumption: 150mW at 1.8V(2)
- Universal clock input
- Differential AC-coupled or LVCMOS: 1MHz to 250MHz
- Crystal: 8MHz to 50MHz
- Flexible output frequencies
- 44.1kHz to 350MHz
- Glitchless output divider switching
- Four individually configurable outputs
- LVCMOS, LVDS or HCSL
- Differential AC-coupled with programmable swing (LVDS-, CML-, LVPECL-compatible)
- Fully integrated PLL, configurable loop bandwidth: 100kHz to 3MHz
- Single or mixed supply operation for level translation: 1.8V, 2.5V and 3.3V
- Configurable GPIOs
- Status signals
- Up to four individual output enables
- Output divider synchronization
- Flexible configuration options
- I2C-compatible interface: up to 400kHz
- Integrated EEPROM with two pages and external select pin
- Only supports 100Ω systems
- Industrial temperature range: –40°C to 85°C
- Small footprint: 24-pin VQFN (4mm × 4mm)
Beschreibung von CDCI6214
The CDCI6214 device is an ultra-low power clock generator. The device selects between two independent reference inputs to a phase-locked loop and generates up to four different frequencies on configurable differential output channels and also a copy of the reference clock on a LVCMOS output channel.
Each of the four output channels has a configurable integer divider. Together with the output muxes, this allows up to five different frequencies. Clock distribution dividers are reset in a deterministic way for clean clock gating and glitch-less update capability. Flexible power-down options allow to optimize the device for lowest power consumption in active and standby operation. Typically four 156.25MHz LVDS outputs consume 150mW at 1.8V. Typical RMS jitter of 386fs for 100MHz HCSL output enhances system margin for PCIe applications.
The CDCI6214 is configured using internal registers that are accessed by an I2C-compatible serial interface and internal EEPROM.
The CDCI6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM of the CDCI6214 is designed as an easy-to-use, instant-on clocking feature with low power consumption.