Gehäuseinformationen
| Gehäuse | Pins TSSOP (PW) | 24 |
| Betriebstemperaturbereich (°C) 0 to 85 |
| Gehäusemenge | Träger 2.000 | LARGE T&R |
Merkmale von CDCVF2510
- Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
- Spread Spectrum Clock Compatible
- Operating Frequency 50 MHz to 175 MHz
- Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps
- Jitter (cyc - cyc) at 66 MHz to 166 MHz Is |70| ps
- Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices
- Available in Plastic 24-Pin TSSOP
- Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
- Distributes One Clock Input to One Bank of 10 Outputs
- External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
- 25-
On-Chip Series Damping Resistors - No External RC Network Required
- Operates at 3.3 V
NOT RECOMMENDED FOR NEW DESIGNS USE CDCVF2510A AS A REPLACEMENT
Beschreibung von CDCVF2510
The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510 operates at a 3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDCVF2510 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDCVF2510 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, a fixed-phase signal at CLK, or following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
The CDCVF2510 is characterized for operation from 0°C to 85°C.
For application information see the application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (SLMA003) and Using CDC2509A/2510A PLL With Spread Spectrum Clocking (SSC) (SCAA039).