Produktdetails

Coprocessors 2 Dual Arm Cortex-M4 Display type 1 LCD OUT, 1 SD-DAC Protocols Ethernet PCIe 2 PCIe Gen2 Hardware accelerators 1 Audio Tracking Logic Features Multimedia Operating system Android, Linux, RTOS TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution LP873220-Q1, LP87332D-Q1, TPS65917-Q1, TPS65919-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled No
Coprocessors 2 Dual Arm Cortex-M4 Display type 1 LCD OUT, 1 SD-DAC Protocols Ethernet PCIe 2 PCIe Gen2 Hardware accelerators 1 Audio Tracking Logic Features Multimedia Operating system Android, Linux, RTOS TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution LP873220-Q1, LP87332D-Q1, TPS65917-Q1, TPS65919-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled No
FCBGA (ABF) 367 225 mm² (15 mm × 15 mm)
  • Architecture designed for infotainment applications
  • Up to 2 C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512kB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • Memory Interface (EMIF) module
    • Supports DDR3/DDR3L up to DDR-1066
    • Supports DDR2 up to DDR-800
    • Up to 2GB supported
  • Dual Arm® Cortex®-M4 (IPU)
  • Vision accelerationPac
    • Embedded Vision Engine (EVE)
  • Display subsystem
    • Display controller with DMA engine
    • CVIDEO / SD-DAC TV analog composite output
  • On-chip temperature sensor that is capable of generating temperature alerts
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 3-port (2 external) Gigabit Ethernet (GMAC) switch
  • Controller Area Network (DCAN) module
    • CAN 2.0B protocol
  • Modular Controller Area Network (MCAN) module
    • CAN 2.0B protocol
  • Eight 32-bit general-purpose timers
  • Three configurable UART modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI interface
  • Two Inter-Integrated Circuit (I2C™) ports
  • Three Multichannel Audio Serial Port (McASP) modules
  • Secure Digital Input Output Interface (SDIO)
  • Up to 126 General-Purpose I/O (GPIO) pins
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • Automotive AEC-Q100 qualified
  • 15 × 15 mm, 0.65-mm pitch, 367-pin PBGA (ABF)
  • Five instances of Real-Time Interrupt (RTI) modules that can be used as watch dog timers
  • 8-channel 10-bit ADC
  • PWMSS
  • Video and image processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Video input and video output
    • GPIOs when not used for video
  • Video Input Port (VIP) module
    • Support for up to 4 multiplexed input ports
  • Architecture designed for infotainment applications
  • Up to 2 C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512kB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • Memory Interface (EMIF) module
    • Supports DDR3/DDR3L up to DDR-1066
    • Supports DDR2 up to DDR-800
    • Up to 2GB supported
  • Dual Arm® Cortex®-M4 (IPU)
  • Vision accelerationPac
    • Embedded Vision Engine (EVE)
  • Display subsystem
    • Display controller with DMA engine
    • CVIDEO / SD-DAC TV analog composite output
  • On-chip temperature sensor that is capable of generating temperature alerts
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 3-port (2 external) Gigabit Ethernet (GMAC) switch
  • Controller Area Network (DCAN) module
    • CAN 2.0B protocol
  • Modular Controller Area Network (MCAN) module
    • CAN 2.0B protocol
  • Eight 32-bit general-purpose timers
  • Three configurable UART modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI interface
  • Two Inter-Integrated Circuit (I2C™) ports
  • Three Multichannel Audio Serial Port (McASP) modules
  • Secure Digital Input Output Interface (SDIO)
  • Up to 126 General-Purpose I/O (GPIO) pins
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • Automotive AEC-Q100 qualified
  • 15 × 15 mm, 0.65-mm pitch, 367-pin PBGA (ABF)
  • Five instances of Real-Time Interrupt (RTI) modules that can be used as watch dog timers
  • 8-channel 10-bit ADC
  • PWMSS
  • Video and image processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Video input and video output
    • GPIOs when not used for video
  • Video Input Port (VIP) module
    • Support for up to 4 multiplexed input ports

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8 mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8 mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt DRA78x Infotainment Applications Processor datasheet (Rev. H) PDF | HTML 04.02.2020
* Benutzerhandbuch DRA78x Technical Reference Manual (Rev. D) 30.07.2019
* Errata DRA78x Silicon Errata (Rev. B) 01.10.2019
Anwendungshinweis Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC PDF | HTML 05.05.2021
Anwendungshinweis IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC PDF | HTML 24.08.2020
Anwendungshinweis AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 06.01.2020
Anwendungshinweis Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 11.06.2019
Anwendungshinweis Achieving Early CAN Response on DRA7xx Devices 28.11.2018
Anwendungshinweis DRA74x_75x/DRA72x Performance (Rev. A) 31.10.2018
Anwendungshinweis Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices 14.09.2018
Anwendungshinweis The Implementation of YUV422 Output for SRV 02.08.2018
Anwendungshinweis MMC DLL Tuning (Rev. B) 31.07.2018
Anwendungshinweis Integrating AUTOSAR on TI SoC: Fundamentals 18.06.2018
Anwendungshinweis ECC/EDC on TDAxx (Rev. B) 13.06.2018
Anwendungshinweis Tools and Techniques to Root Case Failures in Video Capture Subsystem 12.06.2018
Anwendungshinweis Sharing VPE Between VISIONSDK and PSDKLA 04.05.2018
Anwendungshinweis Android Boot Optimization on DRA7xx Devices (Rev. A) 13.02.2018
Anwendungshinweis Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) 30.11.2017
Anwendungshinweis Jacinto6 Spread Spectrum Clocking Configuration (Rev. A) 27.11.2017
Anwendungshinweis Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 07.11.2017
Anwendungshinweis A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 03.11.2017
Anwendungshinweis Optimization of GPU-Based Surround View on TI’s TDA2x SoC 12.09.2017
Anwendungshinweis Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices 14.08.2017
Anwendungshinweis Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices 12.07.2017
Anwendungshinweis Linux Boot Time Optimizations on DRA7xx Devices 31.03.2017
Anwendungshinweis Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) 17.02.2017
Anwendungshinweis Early Splash Screen on DRA7x Devices 31.01.2017
Anwendungshinweis Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 15.12.2016
Anwendungshinweis Gstreamer Migration Guidelines 26.04.2016
Anwendungshinweis Flashing Binaries to DRA7xx Factory Boards Using DFU 14.04.2016
Anwendungshinweis Tools and Techniques for Audio Debugging 13.04.2016
Anwendungshinweis Debugging Tools and Techniques With IPC3.x 30.03.2016
Anwendungshinweis Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) 15.01.2016
Whitepaper Informational ADAS as Software Upgrade to Today’s Infotainment Systems 14.10.2014
Anwendungshinweis Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 13.08.2014
Whitepaper Today’s high-end infotainment soon becoming mainstream 02.06.2014

Design und Entwicklung

Lösungen für die Stromversorgung

Verfügbare Lösungen für die Stromversorgung für den DRA782 finden. TI bietet Stromversorgungslösungen für Ein-Chip-Systeme (SoCs), Prozessoren, Mikrocontroller, Sensoren und feldprogrammierbare Gate-Arrays (FPGAs) von TI und von Fremdherstellern an.

Evaluierungsplatine

DRA78XEVM — DRA78x-Evaluierungsmodul

The Jacinto™ DRA78x evaluation module (EVM) is an evaluation platform designed to speed up development efforts and reduce time-to-market for Radio Signal Processor (RSP) applications. The EVM is based on the Jacinto DRA78x SoC, which incorporates a heterogeneous, scalable architecture (...)

Benutzerhandbuch: PDF
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Debug-Tastkopf

LB-3P-TRACE32-DSP — Debug- und Trace-System Lauterbach TRACE32 für digitale Signalprozessoren (Digital Signal Processors

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-ANDROID-AUTOMOTIVE-DRA7X

Prozessor-SDK Linux Automotive

Das Prozessor-SDK Linux Automotive ist die grundlegende Software-Entwicklungsplattform für die Jacinto™ DRAx-Familie der Infotainment-SoCs von TI. Mit dem Software-Framework können Infotainment-Lösungen mit großem Funktionsumfang entwickelt werden. Dazu zählen (...)

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X — PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X

Prozessor-SDK Linux Automotive

Das Prozessor-SDK Linux Automotive ist die grundlegende Software-Entwicklungsplattform für die Jacinto™ DRAx-Familie der Infotainment-SoCs von TI. Mit dem Software-Framework können Infotainment-Lösungen mit großem Funktionsumfang entwickelt werden. Dazu zählen (...)

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-RTOS-AUTOMOTIVE-DRA7X

Prozessor-SDK Linux Automotive

Das Prozessor-SDK Linux Automotive ist die grundlegende Software-Entwicklungsplattform für die Jacinto™ DRAx-Familie der Infotainment-SoCs von TI. Mit dem Software-Framework können Infotainment-Lösungen mit großem Funktionsumfang entwickelt werden. Dazu zählen (...)

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IDE, Konfiguration, Compiler oder Debugger

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

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Betriebssystem (BS)

GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
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Support-Software

VCTR-3P-MICROSAR — Vector MICROSAR AUTOSAR-Software für Mikrocontroller und Hochleistungscomputer (HPCs)

Die MICROSAR- und DaVinci-Produktfamilien vereinfachen die Steuergeräte-Entwicklung mit ausgefeilter Embedded-Software und leistungsstarken Entwicklungswerkzeugen für Mikrocontroller und HPCs. Mit fortschrittlicher Infrastruktursoftware schaffen Sie eine optimale Basis für Ihre Steuergeräte und (...)

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Simulationsmodell

DRA78x BSDL Model

SPRM713.ZIP (9 KB) - BSDL-Modell
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Simulationsmodell

DRA78x IBIS Model

SPRM703.ZIP (10940 KB) - IBIS-Modell
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Simulationsmodell

DRA78x Thermal Model

SPRM704.ZIP (1 KB) - Wärmemodell
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Berechnungstool

CLOCKTREETOOL — Taktbaum-Tool für Sitara, Automobilanwendungen, Sichtanalytik und digitale Signalprozessoren

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
Unterstützte Produkte und Hardware
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
FCBGA (ABF) 367 Ultra Librarian

Bestellen & Qualität

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