Detalles del producto

Technology family CD4000 Number of channels 1 Operating temperature range (°C) -55 to 125 Rating Catalog Supply current (max) (µA) 3000
Technology family CD4000 Number of channels 1 Operating temperature range (°C) -55 to 125 Rating Catalog Supply current (max) (µA) 3000
PDIP (N) 16 181.42 mm² (19.3 mm × 9.4 mm) SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm) SOP (NS) 16 79.56 mm² (10.2 mm × 7.8 mm)
  • Display blanking of all illegal input combinations
  • Latch storage of code
  • Capability of driving two low power TTL loads, two HTL loads, or one low power Schottky load over the full rated-temperature range
  • Pin-for-pin replacement for the CD4056B (with pin 7 tied to VSS)
  • Direct LED driving capability
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
    1 V at VDD = 5 V
    2 V at VDD = 10 V
    2.5 V at VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications:
    • Instrument display driver
    • Dashboard display driver
    • Computer/calculator display driver
    • Timing device driver (clocks, watches, timers)

  • Display blanking of all illegal input combinations
  • Latch storage of code
  • Capability of driving two low power TTL loads, two HTL loads, or one low power Schottky load over the full rated-temperature range
  • Pin-for-pin replacement for the CD4056B (with pin 7 tied to VSS)
  • Direct LED driving capability
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
    1 V at VDD = 5 V
    2 V at VDD = 10 V
    2.5 V at VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications:
    • Instrument display driver
    • Dashboard display driver
    • Computer/calculator display driver
    • Timing device driver (clocks, watches, timers)

CD4543B is a BCD-to-seven segment latch/decoder/driver designed primarily for liquid-crystal display (LCD) applications. It is also capable of driving light emitting diode (LED), incandescent, gas-discharge, and fluorescent displays. This device is functionally similar to and serves as direct replacement for the CD4056B when pin 7 is connected to VSS. It differs from the CD4056B in that it has a display blanking capability instead of a level-shifting function and requires only one power supply. When the CD4056B is used in the level shifting mode, two power supplies are required. When the CD4543B is used for LCD applications, a square wave must be applied to the PHASE input and the backplane of the LCD device. For LED applications a logic 1 is required at the PHASE input for common-cathode devices; a logic 0 is required for common-anode devices (see truth table).

The CD4543B is supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4543B is a BCD-to-seven segment latch/decoder/driver designed primarily for liquid-crystal display (LCD) applications. It is also capable of driving light emitting diode (LED), incandescent, gas-discharge, and fluorescent displays. This device is functionally similar to and serves as direct replacement for the CD4056B when pin 7 is connected to VSS. It differs from the CD4056B in that it has a display blanking capability instead of a level-shifting function and requires only one power supply. When the CD4056B is used in the level shifting mode, two power supplies are required. When the CD4543B is used for LCD applications, a square wave must be applied to the PHASE input and the backplane of the LCD device. For LED applications a logic 1 is required at the PHASE input for common-cathode devices; a logic 0 is required for common-anode devices (see truth table).

The CD4543B is supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

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* Hoja de datos CD4543B Types datasheet (Rev. D) 29/04/2004

Diseño y desarrollo

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Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación (EVM) 14-24-LOGIC-EVM está diseñado para admitir cualquier dispositivo lógico que se encuentre en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
PDIP (N) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian

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