DS32EL0421

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Serializador FPGA-link de 125 MHz a 312.5 MHz con interfaz paralela LVDS DDR

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Hoja de datos

document-pdfAcrobat DS32EL0421/ELX0421 125 - 312.5 MHz FPGA-Link Serializer w/ DDR LVDS Parallel I/F datasheet (Rev. F) (Inglés)

DS32EL0421

ACTIVO

Hoja de datos

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Detalles del producto

Protocols

Catalog

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Protocols

Catalog

Rating

Catalog

Operating temperature range (°C)

-40 to 85

WQFN (RHS)

48

49 mm² (7 mm × 7 mm)

5-bit DDR LVDS Parallel Data Interface
Programmable Transmit De-emphasis
Configurable Output Levels (V_OD)
Selectable DC-balanced Encoder
Selectable Data Scrambler
Remote Sense for Automatic Detection and Negotiation of Link Status
On Chip LC VCOs
Redundant Serial Output (ELX device only)
Data Valid Signaling to Assist with Synchronization of Multiple Receivers
Supports AC- and DC-coupled Signaling
Integrated CML and LVDS Terminations
Configurable PLL Loop Bandwidth
Programmable Output Termination (50Ω or 75Ω).
Built-in Test Pattern Generator
Loss of Lock and Error Reporting
Configurable via SMBus
48-pin WQFN Package with Exposed DAP

Key Specifications

1.25 to 3.125 Gbps Serial Data Rate
125 to 312.5 MHz DDR Parallel Clock
-40° to +85°C Temperature Range
>8 kV ESD (HBM) Protection
Low Intrinsic Jitter — 35ps at 3.125 Gbps

All trademarks are the property of their respective owners.

5-bit DDR LVDS Parallel Data Interface
Programmable Transmit De-emphasis
Configurable Output Levels (V_OD)
Selectable DC-balanced Encoder
Selectable Data Scrambler
Remote Sense for Automatic Detection and Negotiation of Link Status
On Chip LC VCOs
Redundant Serial Output (ELX device only)
Data Valid Signaling to Assist with Synchronization of Multiple Receivers
Supports AC- and DC-coupled Signaling
Integrated CML and LVDS Terminations
Configurable PLL Loop Bandwidth
Programmable Output Termination (50Ω or 75Ω).
Built-in Test Pattern Generator
Loss of Lock and Error Reporting
Configurable via SMBus
48-pin WQFN Package with Exposed DAP

Key Specifications

1.25 to 3.125 Gbps Serial Data Rate
125 to 312.5 MHz DDR Parallel Clock
-40° to +85°C Temperature Range
>8 kV ESD (HBM) Protection
Low Intrinsic Jitter — 35ps at 3.125 Gbps

All trademarks are the property of their respective owners.

The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.

The DS32EL0421/DS32ELX0421 serializes up to 5 parallel input LVDS channels to create a maximum data payload of 3.125 Gbps. If the integrated DC-balance encoding is enabled, the maximum data payload achievable is 2.5 Gbps.

The DS32EL0421/DS32ELX0421 serializers feature remote sense capability to automatically detect and negotiate link status with its companion DS32EL0124/DS32ELX0124 deserializers without requiring an additional feedback path.

The parallel LVDS interface reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.

The DS32EL0421/DS32ELX0421 is programmable through a SMBus interface as well as through control pins.

The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.

The DS32EL0421/DS32ELX0421 serializes up to 5 parallel input LVDS channels to create a maximum data payload of 3.125 Gbps. If the integrated DC-balance encoding is enabled, the maximum data payload achievable is 2.5 Gbps.

The DS32EL0421/DS32ELX0421 serializers feature remote sense capability to automatically detect and negotiate link status with its companion DS32EL0124/DS32ELX0124 deserializers without requiring an additional feedback path.

The parallel LVDS interface reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.

The DS32EL0421/DS32ELX0421 is programmable through a SMBus interface as well as through control pins.

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Documentación técnica

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Documentación principal	Tipo	Título	Fecha
*	Hoja de datos	DS32EL0421/ELX0421 125 - 312.5 MHz FPGA-Link Serializer w/ DDR LVDS Parallel I/F datasheet (Rev. F)	15/04/2013
	Nota sobre la aplicación	LVDS Timing DS32ELX0421 and DS32ELX0124 Serializers and Deserializers (Rev. A)	26/04/2013
	Nota sobre la aplicación	Expanding the Payload w/FPGA-Link DS32ELX0421 and DS32ELX0124 SER/DES (Rev. A)	26/04/2013

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

DS32ELX0421 IBIS Model

SNLM198.ZIP (52 KB) - Modelo IBIS

Productos y hardware compatibles

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Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
WQFN (RHS)	48	Ultra Librarian

Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

DS32EL0421

Serializador FPGA-link de 125 MHz a 312.5 MHz con interfaz paralela LVDS DDR

DS32EL0421

Detalles del producto

Key Specifications

Key Specifications

Documentación técnica

Diseño y desarrollo

DS32ELX0421 IBIS Model

Pedidos y calidad

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Serie de videos

Videos