Inicio Interfaz Serializadores-deserializadores de alta velocidad Serializadores-deserializadores FPD-Link
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Interfaz
Serializadores-deserializadores de alta velocidad
Serializadores-deserializadores FPD-Link

DS90C241-Q1

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Sserializador FPD-Link II de 5 MHz a 35 MHz y 24 bits con equilibrio DC para automoción

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DS90C241-Q1

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Detalles del producto

Applications In-vehicle Infotainment (IVI) Input compatibility LVCMOS Function Serializer Output compatibility FPD-Link LVDS Color depth (bpp) 18 Features Low-EMI Point-to-Point Communication Rating Automotive Operating temperature range (°C) -40 to 105
Applications In-vehicle Infotainment (IVI) Input compatibility LVCMOS Function Serializer Output compatibility FPD-Link LVDS Color depth (bpp) 18 Features Low-EMI Point-to-Point Communication Rating Automotive Operating temperature range (°C) -40 to 105
TQFP (PFB) 48 81 mm² (9 mm × 9 mm)
  • 5-MHz to 35-MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
  • User Defined Pre-Emphasis Driving Ability Through External Resistor on LVDS Outputs and Capable to Drive Up to 10-Meter Shielded Twisted-Pair Cable
  • User-Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver
  • Internal DC Balancing Encode and Decode (Supports AC-Coupling Interface With No External Coding Required)
  • Individual Power-Down Controls for Both Transmitter and Receiver
  • Embedded Clock CDR (Clock and Data Recovery) on Receiver and No External Source of Reference Clock Required
  • All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
  • LOCK Output Flag to Ensure Data Integrity at Receiver Side
  • Balanced TSETUP and THOLD Between RCLK and RDATA on Receiver Side
  • PTO (Progressive Turnon) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
  • All LVCMOS Inputs and Control Pins Have Internal Pulldown
  • On-Chip Filters for PLLs on Transmitter and Receiver
  • Temperature Range: –40°C to 105°C
  • Greater Than 8-kV HBM ESD Tolerant
  • Meets AEC-Q100 Compliance
  • Power Supply Range: 3.3 V ± 10%
  • 48-Pin TQFP Package
  • 5-MHz to 35-MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
  • User Defined Pre-Emphasis Driving Ability Through External Resistor on LVDS Outputs and Capable to Drive Up to 10-Meter Shielded Twisted-Pair Cable
  • User-Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver
  • Internal DC Balancing Encode and Decode (Supports AC-Coupling Interface With No External Coding Required)
  • Individual Power-Down Controls for Both Transmitter and Receiver
  • Embedded Clock CDR (Clock and Data Recovery) on Receiver and No External Source of Reference Clock Required
  • All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
  • LOCK Output Flag to Ensure Data Integrity at Receiver Side
  • Balanced TSETUP and THOLD Between RCLK and RDATA on Receiver Side
  • PTO (Progressive Turnon) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
  • All LVCMOS Inputs and Control Pins Have Internal Pulldown
  • On-Chip Filters for PLLs on Transmitter and Receiver
  • Temperature Range: –40°C to 105°C
  • Greater Than 8-kV HBM ESD Tolerant
  • Meets AEC-Q100 Compliance
  • Power Supply Range: 3.3 V ± 10%
  • 48-Pin TQFP Package

The DS90C241 and DS90C124 chipset translates a 24-bit parallel bus into a fully transparent data and control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces or over cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths, which in turn reduces PCB layers, cable width, and connector size and pins.

The DS90C241 and DS90C124 incorporate LVDS signaling on the high-speed I/O. LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range, EMI is further reduced.

In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding and decoding supports AC-coupled interconnects.

The DS90C241 and DS90C124 chipset translates a 24-bit parallel bus into a fully transparent data and control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces or over cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths, which in turn reduces PCB layers, cable width, and connector size and pins.

The DS90C241 and DS90C124 incorporate LVDS signaling on the high-speed I/O. LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range, EMI is further reduced.

In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding and decoding supports AC-coupled interconnects.
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos DS90C241 and DS90C124 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer datasheet (Rev. M) PDF | HTML 3/01/2017
Nota sobre la aplicación LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) 29/04/2013
Nota sobre la aplicación Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A) 26/04/2013
Guía del usuario SERDES24-35OVT Evaluation Kit for OV7710 Image Sensor Application w/ a FPD-Link 23/02/2012
Guía del usuario DS90C241/DS90C124 FPD- Link II Embedded Clock LVDS SerDes EVK User Guide 26/01/2012
Guía del usuario DS90UR241/DS90UR124 SERDES Evaluation Kit User's Guide 26/01/2012

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