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Circuitos integrados LVDS, M-LVDS y PECL

DS90LV804

ACTIVO

Búfer/repetidor LVDS de 4 canales y 800 Mbps

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DS90LV804

ACTIVO
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Detalles del producto

Function Buffer Protocols LVDS Number of transmitters 4 Number of receivers 4 Signaling rate (Mbps) 800 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Buffer Protocols LVDS Number of transmitters 4 Number of receivers 4 Signaling rate (Mbps) 800 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
WQFN (RTV) 32 25 mm² (5 mm × 5 mm)
  • 800 Mbps Data Rate per Channel
  • Low Output Skew and Jitter
  • LVDS/CML/LVPECL Compatible Input, LVDS Output
  • On-Chip 100Ω Input and Output Termination
  • 12 kV ESD Protection on LVDS Outputs
  • Single 3.3V Supply
  • Very Low Power Consumption
  • Industrial -40 to +85°C Temperature Range
  • Small WQFN Package Footprint

All trademarks are the property of their respective owners.

  • 800 Mbps Data Rate per Channel
  • Low Output Skew and Jitter
  • LVDS/CML/LVPECL Compatible Input, LVDS Output
  • On-Chip 100Ω Input and Output Termination
  • 12 kV ESD Protection on LVDS Outputs
  • Single 3.3V Supply
  • Very Low Power Consumption
  • Industrial -40 to +85°C Temperature Range
  • Small WQFN Package Footprint

All trademarks are the property of their respective owners.

The DS90LV804 is a four channel 800 Mbps LVDS buffer/repeater. In many large systems, signals are distributed across cables and signal integrity is highly dependent on the data rate, cable type, length, and the termination scheme.

In order to maximize signal integrity, the DS90LV804 features both an internal input and output (source) termination to eliminate these extra components from the board, and to also place the terminations as close as possible to receiver inputs and driver output. This is especially significant when driving longer cables.

The DS90LV804, available in the WQFN (Leadless Leadframe Package) package, minimizes the footprint, and improves system performance.

An output enable pin is provided, which allows the user to place the LVDS outputs and internal biasing generators in a TRI-STATE, low power mode.

The differential inputs interface to LVDS, and Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs are internally terminated with a 100Ω resistor to improve performance and minimize board space. This function is especially useful for boosting signals over lossy cables or point-to-point backplane configurations.

The DS90LV804 is a four channel 800 Mbps LVDS buffer/repeater. In many large systems, signals are distributed across cables and signal integrity is highly dependent on the data rate, cable type, length, and the termination scheme.

In order to maximize signal integrity, the DS90LV804 features both an internal input and output (source) termination to eliminate these extra components from the board, and to also place the terminations as close as possible to receiver inputs and driver output. This is especially significant when driving longer cables.

The DS90LV804, available in the WQFN (Leadless Leadframe Package) package, minimizes the footprint, and improves system performance.

An output enable pin is provided, which allows the user to place the LVDS outputs and internal biasing generators in a TRI-STATE, low power mode.

The differential inputs interface to LVDS, and Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs are internally terminated with a 100Ω resistor to improve performance and minimize board space. This function is especially useful for boosting signals over lossy cables or point-to-point backplane configurations.
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Documentación técnica

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Ver todo 4
Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos DS90LV804 4-Channel 800 Mbps LVDS Buffer/Repeater datasheet (Rev. L) 16/05/2013
Nota sobre la aplicación Signaling Rate vs. Distance for Differential Buffers 26/01/2010
Informe Making the Most of Your LVDS - 5 Tips for Buffering Signal Integrity Headaches 1/08/2001
Nota sobre la aplicación An Overview of LVDS Technology 5/10/1998

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

DS90LV804 IBIS Model

SNLM025.ZIP (11 KB) - Modelo IBIS
Productos y hardware compatibles
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
WQFN (RTV) 32 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

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Soporte y capacitación

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