Inicio Interfaz Circuitos integrados LVDS, M-LVDS y PECL

DS91D180

ACTIVO

Par de controlador/receptor de línea M-LVDS de 100 MHz

Detalles del producto

Function Transceiver Protocols M-LVDS Number of transmitters 1 Number of receivers 1 Signaling rate (Mbps) 200 Input signal LVTTL, M-LVDS Output signal LVTTL, M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Transceiver Protocols M-LVDS Number of transmitters 1 Number of receivers 1 Signaling rate (Mbps) 200 Input signal LVTTL, M-LVDS Output signal LVTTL, M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm)
  • DC to 100+ MHz / 200+ Mbps Low Power, Low EMI Operation
  • Optimal for ATCA, uTCA Clock Distribution Networks
  • Meets or Exceeds TIA/EIA-899 M-LVDS Standard
  • Wide Input Common Mode Voltage for Increased Noise Immunity
  • DS91D180 has Type 1 Receiver Input
  • DS91C180 has Type 2 Receiver Input for Fail-Safe Functionality
  • Industrial Temperature Range
  • Space Saving SOIC-14 Package (JEDEC MS-012)

All trademarks are the property of their respective owners.

  • DC to 100+ MHz / 200+ Mbps Low Power, Low EMI Operation
  • Optimal for ATCA, uTCA Clock Distribution Networks
  • Meets or Exceeds TIA/EIA-899 M-LVDS Standard
  • Wide Input Common Mode Voltage for Increased Noise Immunity
  • DS91D180 has Type 1 Receiver Input
  • DS91C180 has Type 2 Receiver Input for Fail-Safe Functionality
  • Industrial Temperature Range
  • Space Saving SOIC-14 Package (JEDEC MS-012)

All trademarks are the property of their respective owners.

The DS91D180 and DS91C180 are 100 MHz M-LVDS (Multipoint Low Voltage Differential Signaling) line driver/receiver pairs designed for applications that utilize multipoint networks (e.g. clock distribution in ATCA and uTCA based systems). M-LVDS is a bus interface standard (TIA/EIA-899) optimized for multidrop networks. Controlled edge rates, tight input receiver thresholds and increased drive strength are sone of the key enhancments that make M-LVDS devices an ideal choice for distributing signals via multipoint networks.

The DS91D180/DS91C180 driver input accepts LVTTL/LVCMOS signals and converts them to differential M-LVDS signal levels. The DS91D180/DS91C180 receiver accepts low voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL and CML) and converts them to 3V LVCMOS signals. The DS91D180 device has a M-LVDS type 1 receiver input with no offset.The DS91C180 device has a type 2 receiver input which enable failsafe functionality.

The DS91D180 and DS91C180 are 100 MHz M-LVDS (Multipoint Low Voltage Differential Signaling) line driver/receiver pairs designed for applications that utilize multipoint networks (e.g. clock distribution in ATCA and uTCA based systems). M-LVDS is a bus interface standard (TIA/EIA-899) optimized for multidrop networks. Controlled edge rates, tight input receiver thresholds and increased drive strength are sone of the key enhancments that make M-LVDS devices an ideal choice for distributing signals via multipoint networks.

The DS91D180/DS91C180 driver input accepts LVTTL/LVCMOS signals and converts them to differential M-LVDS signal levels. The DS91D180/DS91C180 receiver accepts low voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL and CML) and converts them to 3V LVCMOS signals. The DS91D180 device has a M-LVDS type 1 receiver input with no offset.The DS91C180 device has a type 2 receiver input which enable failsafe functionality.

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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos DS91D180/DS91C180 100 MHz M-LVDS Line Driver/Receiver Pair datasheet (Rev. M) 18/04/2013
Application brief How Far, How Fast Can You Operate MLVDS? 6/08/2018
Nota sobre la aplicación Designing an ATCA Compliant M-LVDS Clock Distribution Network (Rev. B) 26/04/2013
Nota sobre la aplicación Introduction to M-LVDS (TIA/EIA-899) (Rev. A) 3/01/2013

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