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Circuitos integrados LVDS, M-LVDS y PECL

DS92LV090A

ACTIVO

Transceptor LVDS de bus de 9 canales

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DS92LV090A

ACTIVO
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Detalles del producto

Function Transceiver Protocols BLVDS Number of transmitters 9 Number of receivers 9 Signaling rate (Mbps) 100 Input signal BLVDS, LVTTL Output signal BLVDS, CMOS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Transceiver Protocols BLVDS Number of transmitters 9 Number of receivers 9 Signaling rate (Mbps) 100 Input signal BLVDS, LVTTL Output signal BLVDS, CMOS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
LQFP (PM) 64 144 mm² (12 mm × 12 mm)
  • Bus LVDS Signaling
  • 3.2 Nanosecond Propagation Delay Max
  • Chip to Chip Skew ±800ps
  • Low Power CMOS Design
  • High Signaling Rate Capability (Above 100 Mbps)
  • 0.1V to 2.3V Common Mode Range for VID = 200mV
  • ±100 mV Receiver Sensitivity
  • Supports Open and Terminated Failsafe on Port Pins
  • 3.3V Operation
  • Glitch Free Power Up/Down (Driver & Receiver Disabled)
  • Light Bus Loading (5 pF Typical) per Bus LVDS Load
  • Designed for Double Termination Applications
  • Balanced Output Impedance
  • Product Offered in 64 Pin LQFP Package
  • High Impedance Bus Pins on Power off (VCC = 0V)
  • Driver Channel to Channel Skew (Same Device) 230ps Typical
  • Receiver Channel to Channel Skew (Same Device) 370ps Typical

All trademarks are the property of their respective owners.

  • Bus LVDS Signaling
  • 3.2 Nanosecond Propagation Delay Max
  • Chip to Chip Skew ±800ps
  • Low Power CMOS Design
  • High Signaling Rate Capability (Above 100 Mbps)
  • 0.1V to 2.3V Common Mode Range for VID = 200mV
  • ±100 mV Receiver Sensitivity
  • Supports Open and Terminated Failsafe on Port Pins
  • 3.3V Operation
  • Glitch Free Power Up/Down (Driver & Receiver Disabled)
  • Light Bus Loading (5 pF Typical) per Bus LVDS Load
  • Designed for Double Termination Applications
  • Balanced Output Impedance
  • Product Offered in 64 Pin LQFP Package
  • High Impedance Bus Pins on Power off (VCC = 0V)
  • Driver Channel to Channel Skew (Same Device) 230ps Typical
  • Receiver Channel to Channel Skew (Same Device) 370ps Typical

All trademarks are the property of their respective owners.

The DS92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector.

The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of ±1V.

The receiver threshold is less than ±100 mV over a ±1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels. (See Section for more details.)

The DS92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector.

The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of ±1V.

The receiver threshold is less than ±100 mV over a ±1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels. (See Section for more details.)
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Documentación técnica

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* Hoja de datos DS92LV090A 9 Channel Bus LVDS Transceiver datasheet (Rev. D) 19/05/2013

Diseño y desarrollo

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Modelo de simulación

DS92LV090A IBIS Model

SNLM036.ZIP (15 KB) - Modelo IBIS
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LQFP (PM) 64 Ultra Librarian
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