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LP2996-N

ACTIVO

Regulador de terminación DDR de 1,5 A con pin de desconexión para DDR2

Detalles del producto

Product type DDR Vin (min) (V) 1.8 Vin (max) (V) 5.5 Vout (min) (V) 0.656 Vout (max) (V) 0.698 Features Shutdown Pin for S3 Rating Catalog Operating temperature range (°C) 0 to 125 Iq (typ) (mA) 0.32 DDR memory type DDR, DDR2
Product type DDR Vin (min) (V) 1.8 Vin (max) (V) 5.5 Vout (min) (V) 0.656 Vout (max) (V) 0.698 Features Shutdown Pin for S3 Rating Catalog Operating temperature range (°C) 0 to 125 Iq (typ) (mA) 0.32 DDR memory type DDR, DDR2
SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm) WQFN (NHP) 16 16 mm² (4 mm × 4 mm) HSOIC (DDA) 8 29.4 mm² (4.9 mm × 6 mm)
  • Minimum VDDQ:
    • 1.8 V (LP2996-N)
    • 1.35 V (LP2996A)
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required for Setting Output Voltage
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Stable With Ceramic Capacitors With Appropriate ESR
  • Low External Component Count
  • Thermal Shutdown
  • Minimum VDDQ:
    • 1.8 V (LP2996-N)
    • 1.35 V (LP2996A)
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required for Setting Output Voltage
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Stable With Ceramic Capacitors With Appropriate ESR
  • Low External Component Count
  • Thermal Shutdown

The LP2996-N and LP2996A linear regulators are designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, while LP2996A supports DDR3 and DDR3L VTT bus termination with VDDQ minimum of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5-A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2996-N and LP2996A also incorporate a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2996-N and LP2996A is an active-low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but VREF remains active. A power savings advantage can be obtained in this mode through lower quiescent current.

TI recommends the LP2998 and LP2998-Q1 devices for automotive applications and DDR applications that require operating at temperatures below zero.

WEBENCH® design tools can be used by application designers to generate, optimize, and simlulate applications using the LP2998 and LP2998-Q1.

The LP2996-N and LP2996A linear regulators are designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, while LP2996A supports DDR3 and DDR3L VTT bus termination with VDDQ minimum of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5-A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2996-N and LP2996A also incorporate a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2996-N and LP2996A is an active-low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but VREF remains active. A power savings advantage can be obtained in this mode through lower quiescent current.

TI recommends the LP2998 and LP2998-Q1 devices for automotive applications and DDR applications that require operating at temperatures below zero.

WEBENCH® design tools can be used by application designers to generate, optimize, and simlulate applications using the LP2998 and LP2998-Q1.

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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos LP2996/LP2996A DDR Termination Regulator datasheet (Rev. K) PDF | HTML 23/12/2016
Nota sobre la aplicación Limiting DDR Termination Regulators’ Inrush Current 23/08/2016

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

LP2996LQEVAL — Regulador de terminación DDR

The LP2996 evaluation board is designed to provide the design engineer with a fully functional prototype system in which to evaluate the LP2996 in both a static environment and with a complete memory system. There are two versions of the board, and while identical in functionality they differ in (...)

Guía del usuario: PDF
Productos y hardware compatibles
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Modelo de simulación

LP2996-N PSpice Transient Model

SNOM563.ZIP (82 KB) - Modelo PSpice
Productos y hardware compatibles
Modelo de simulación

LP2996-N Unencrypted PSpice Transient Model

SNOM566.ZIP (7 KB) - Modelo PSpice
Productos y hardware compatibles
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (D) 8 Ultra Librarian
WQFN (NHP) 16 Ultra Librarian
HSOIC (DDA) 8 Ultra Librarian

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