SCANSTA112

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Multiplexor IEEE 1149.1 (JTAG) multicaída de 7 puertos

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Hoja de datos

document-pdfAcrobat SCANSTA112 7-Port Multidrop IEEE 1149.1 (JTAG) Multiplexer datasheet (Rev. I) (Inglés)

SCANSTA112

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Hoja de datos

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Detalles del producto

Protocols

Catalog

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Protocols

Catalog

Rating

Catalog

Operating temperature range (°C)

-40 to 85

QFP (NEZ)

100

256 mm² (16 mm × 16 mm)

NFBGA (NZD)

100

100 mm² (10 mm × 10 mm)

True IEEE 1149.1 Hierarchical and Multidrop Addressable Capability
The 8 Address Inputs Support up to 249 Unique Slot Addresses, an Interrogation Address, Broadcast Address, and 4 Multi-Cast Group Addresses (Address 000000 is Reserved)
7 IEEE 1149.1-Compatible Configurable Local Scan Ports
Bi-directional Backplane and LSP₀ Ports are Interchangeable Slave Ports
Capable of Ignoring TRST of the Backplane Port when it Becomes the Slave.
Stitcher Mode Bypasses Level 1 and 2 Protocols
Mode Register₀ Allows Local TAPs to be Bypassed, Selected for Insertion into the Scan Chain Individually, or Serially in Groups of Two or Three
Transparent Mode can be Enabled with a Single Instruction to Conveniently Buffer the Backplane IEEE 1149.1 Pins to Those on a Single Local Scan Port
General Purpose Local Port Pass Through Bits are Useful for Delivering Write Pulses for Flash Programming or Monitoring Device Status.
Known Power-Up State
TRST on all Local Scan Ports
32-bit TCK Counter
16-bit LFSR Signature Compactor
Local TAPs can Become TRI-STATE via the OE Input to Allow an Alternate Test Master to Take Control of the Local TAPs (LSP_0-3 have a TRI-STATE Notification Output)
3.0-3.6V V_CC Supply Operation
Supports Live Insertion/Withdrawal

All trademarks are the property of their respective owners.

True IEEE 1149.1 Hierarchical and Multidrop Addressable Capability
The 8 Address Inputs Support up to 249 Unique Slot Addresses, an Interrogation Address, Broadcast Address, and 4 Multi-Cast Group Addresses (Address 000000 is Reserved)
7 IEEE 1149.1-Compatible Configurable Local Scan Ports
Bi-directional Backplane and LSP₀ Ports are Interchangeable Slave Ports
Capable of Ignoring TRST of the Backplane Port when it Becomes the Slave.
Stitcher Mode Bypasses Level 1 and 2 Protocols
Mode Register₀ Allows Local TAPs to be Bypassed, Selected for Insertion into the Scan Chain Individually, or Serially in Groups of Two or Three
Transparent Mode can be Enabled with a Single Instruction to Conveniently Buffer the Backplane IEEE 1149.1 Pins to Those on a Single Local Scan Port
General Purpose Local Port Pass Through Bits are Useful for Delivering Write Pulses for Flash Programming or Monitoring Device Status.
Known Power-Up State
TRST on all Local Scan Ports
32-bit TCK Counter
16-bit LFSR Signature Compactor
Local TAPs can Become TRI-STATE via the OE Input to Allow an Alternate Test Master to Take Control of the Local TAPs (LSP_0-3 have a TRI-STATE Notification Output)
3.0-3.6V V_CC Supply Operation
Supports Live Insertion/Withdrawal

All trademarks are the property of their respective owners.

The SCANSTA112 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA112 supports up to 7 local IEEE1149.1 scan chains which can be accessed individually or combined serially.

Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.

The STA112 has a unique feature in that the backplane port and the LSP0 port are bidirectional. They can be configured to alternatively act as the master or slave port so an alternate test master can take control of the entire scan chain network from the LSP0 port while the backplane port becomes a slave.

The SCANSTA112 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA112 supports up to 7 local IEEE1149.1 scan chains which can be accessed individually or combined serially.

Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.

The STA112 has a unique feature in that the backplane port and the LSP0 port are bidirectional. They can be configured to alternatively act as the master or slave port so an alternate test master can take control of the entire scan chain network from the LSP0 port while the backplane port becomes a slave.

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Documentación técnica

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Ver todo 9

Documentación principal	Tipo	Título	Fecha
*	Hoja de datos	SCANSTA112 7-Port Multidrop IEEE 1149.1 (JTAG) Multiplexer datasheet (Rev. I)	12/04/2013
	Nota sobre la aplicación	Simplified Programming of Altera FPGAs Using CSANSTA111/112 JTAG Scan Chain Mux (Rev. D)	26/04/2013
	Nota sobre la aplicación	AN-1312 SCANSTA111/SCANSTA112 Scan Bridge Timing (Rev. B)	26/04/2013
	Nota sobre la aplicación	AN-1259 SCANSTA112 Designer's Reference (Rev. H)	26/04/2013
	Nota sobre la aplicación	Simplified Program of Xilinx Devices Using a SCANSTA111/112 JTAG Scan Chain Mux (Rev. C)	26/04/2013
	Más documentación	SCANSTA112 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer Evaluation Kit Docume	21/02/2012
	Nota sobre la aplicación	SCANSTA112 Quick Reference Guide	7/01/2010
	Nota sobre la aplicación	JTAG Advanced Capabilities and System Design	19/03/2009
	Nota sobre la aplicación	Partition IEEE 1149.1 SCAN Chains for Manageability!	6/03/2003

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Soporte de software

EVF-WORKBENCH-CONVERTER-SW — EVF Workbench - Converts JTAG SVF to National’s EVF2 SCAN Format

Graphical User Interface tool for conversion of SVF files to Texas Instrument’s EVF2 embedded file format. Zip file includes readme file, license file, and setup program (1.6MB)

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