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SN65LV1023A

ACTIVO

10:1 Transmisor LVDS SerDes de 100 a 660 Mbps

Detalles del producto

Function Serializer Protocols Channel-Link I Supply voltage (V) 3.3 Signaling rate (Mbps) 660 Input signal LVDS Output signal LVCMOS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Serializer Protocols Channel-Link I Supply voltage (V) 3.3 Signaling rate (Mbps) 660 Input signal LVDS Output signal LVCMOS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DB) 28 79.56 mm² 10.2 x 7.8 VQFN (RHB) 32 25 mm² 5 x 5
  • 100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz
    to 66-MHz System Clock
  • Pin-Compatible Superset of DS92LV1023/DS92LV1224
  • Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHz
  • Synchronization Mode for Faster Lock
  • Lock Indicator
  • No External Components Required for PLL
  • 28-Pin SSOP and Space Saving 5 × 5 mm QFN Packages Available
  • Industrial Temperature Qualified,
    TA = −40°C to 85°C
  • Programmable Edge Trigger on Clock
  • Flow-Through Pinout for Easy PCB Layout
  • APPLICATIONS
    • Wireless Base Station
    • Backplane Interconnect
    • DSLAM

  • 100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz
    to 66-MHz System Clock
  • Pin-Compatible Superset of DS92LV1023/DS92LV1224
  • Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHz
  • Synchronization Mode for Faster Lock
  • Lock Indicator
  • No External Components Required for PLL
  • 28-Pin SSOP and Space Saving 5 × 5 mm QFN Packages Available
  • Industrial Temperature Qualified,
    TA = −40°C to 85°C
  • Programmable Edge Trigger on Clock
  • Flow-Through Pinout for Easy PCB Layout
  • APPLICATIONS
    • Wireless Base Station
    • Backplane Interconnect
    • DSLAM

The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput.

Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters.

The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock.

The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of –40°C to 85°C.

The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput.

Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters.

The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock.

The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of –40°C to 85°C.

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Documentación técnica

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Tipo Título Fecha
* Data sheet 10-MHz to 66-MHz, 10:1-LVDS Serializer/Deserializer datasheet (Rev. E) 07 dic 2009
* Errata SN65LV1023A Sync Pattern Generation Logic Error 26 jun 2003
Application note Applications of Low-Voltage Differential Signaling (LVDS) in LED Walls 29 oct 2020
Application brief Migrating from DS92LV1021A/1212A 10-bit SerDes to SN65LV1023A/1224B 15 nov 2018
User guide 10:1 Serializer/Deserializer Evaluation Board 20 nov 2013

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

SN65LV1023A IBIS Model

SLLM358.ZIP (31 KB) - IBIS Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SSOP (DB) 28 Ultra Librarian
VQFN (RHB) 32 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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