SN65LVDS18

ACTIVO

Platina de ganancia/búfer de oscilador de 2.5 V/3.3 V con capacidad de activación

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Hoja de datos

document-pdfAcrobat 2.5-V/3.3-V Oscillator Gain Stage/Buffers datasheet (Rev. B) (Inglés)

SN65LVDS18

ACTIVO

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Detalles del producto

Function

Buffer, Translator

Protocols

LVDS, LVPECL

Number of transmitters

1

Number of receivers

1

Signaling rate (Mbps)

2000

Input signal

Single-ended

Output signal

LVDS

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Function

Buffer, Translator

Protocols

LVDS, LVPECL

Number of transmitters

1

Number of receivers

1

Signaling rate (Mbps)

2000

Input signal

Single-ended

Output signal

LVDS

Rating

Catalog

Operating temperature range (°C)

-40 to 85

WSON (DRF)

8

4 mm² (2 mm × 2 mm)

Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs
Clock Rates to 1 GHz
- 250-ps Output Transition Times
- 0.12 ps Typical Intrinsic Phase Jitter
- Less than 630 ps Propagation Delay Times
2.5-V or 3.3-V Supply Operation
2-mm x 2-mm Small-Outline No-Lead Package
APPLICATIONS
- PECL-to-LVDS Translation
- Clock Signal Amplification

Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs
Clock Rates to 1 GHz
- 250-ps Output Transition Times
- 0.12 ps Typical Intrinsic Phase Jitter
- Less than 630 ps Propagation Delay Times
2.5-V or 3.3-V Supply Operation
2-mm x 2-mm Small-Outline No-Lead Package
APPLICATIONS
- PECL-to-LVDS Translation
- Clock Signal Amplification

These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx18) and fully differential inputs on the SN65LVx19.

The SN65LVx18 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to V_CC. (When left open, the Q output defaults to 575 mV.) The Q on the SN65LVx19 defaults to 575 mV as well.

Both devices provide a voltage reference (V_BB) of typically 1.35 V below V_CC for use in receiving single-ended PECL input signals. When not used, V_BB should be unconnected or open.

All devices are characterized for operation from -40°C to 85°C.

These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx18) and fully differential inputs on the SN65LVx19.

The SN65LVx18 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to V_CC. (When left open, the Q output defaults to 575 mV.) The Q on the SN65LVx19 defaults to 575 mV as well.

Both devices provide a voltage reference (V_BB) of typically 1.35 V below V_CC for use in receiving single-ended PECL input signals. When not used, V_BB should be unconnected or open.

All devices are characterized for operation from -40°C to 85°C.

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SN65LVDS17

ACTIVO

Platina de ganancia/búfer de oscilador de 2.5 V/3.3 V con capacidad de activación Higher signaling rate (4000Mbps)

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Documentación principal	Tipo	Título	Opciones de formato	Descargar la versión más reciente en inglés		Fecha
*	Hoja de datos	2.5-V/3.3-V Oscillator Gain Stage/Buffers datasheet (Rev. B)			18/11/2005

Diseño y desarrollo

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