Inicio Interfaz Circuitos integrados LVDS, M-LVDS y PECL

SN65LVP17

ACTIVO

Platina de ganancia/búfer de oscilador de 2.5 V/3.3 V con capacidad de activación

Detalles del producto

Function Buffer, Translator Protocols LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 2.5, 3.3 Signaling rate (Mbps) 4000 Input signal Differential Output signal LVPECL Rating Catalog Operating temperature range (°C) -40 to 85
Function Buffer, Translator Protocols LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 2.5, 3.3 Signaling rate (Mbps) 4000 Input signal Differential Output signal LVPECL Rating Catalog Operating temperature range (°C) -40 to 85
WSON (DRF) 8 4 mm² 2 x 2
  • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs
  • Clock Rates to 2 GHz
    • 140-ps Output Transition Times
    • 0.11 ps Typical Intrinsic Phase Jitter
    • Less than 630 ps Propagation Delay Times
  • 2.5-V or 3.3-V Supply Operation
  • 2-mm × 2-mm Small-Outline No-Lead Package
  • APPLICATIONS
    • PECL-to-LVDS Translation
    • Clock Signal Amplification

  • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs
  • Clock Rates to 2 GHz
    • 140-ps Output Transition Times
    • 0.11 ps Typical Intrinsic Phase Jitter
    • Less than 630 ps Propagation Delay Times
  • 2.5-V or 3.3-V Supply Operation
  • 2-mm × 2-mm Small-Outline No-Lead Package
  • APPLICATIONS
    • PECL-to-LVDS Translation
    • Clock Signal Amplification

These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17.

The SN65LVx16 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, the Q output defaults to 575 mV.) The Q on the SN65LVx17 defaults to 575 mV as well.

Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended PECL input signals. When not used, VBB should be unconnected or open.

All devices are characterized for operation from -40°C to 85°C.

These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17.

The SN65LVx16 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, the Q output defaults to 575 mV.) The Q on the SN65LVx17 defaults to 575 mV as well.

Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended PECL input signals. When not used, VBB should be unconnected or open.

All devices are characterized for operation from -40°C to 85°C.

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Documentación técnica

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Tipo Título Fecha
* Data sheet 2.5-V/3.3-V Oscillator Gain Stage/Buffers datasheet (Rev. B) 18 nov 2005
EVM User's guide Translator/Oscillator Buffer EVM (Rev. A) 17 sep 2004

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

SN65LVP17 with Gain Control GC tied to GND IBIS Model

SLLC235.ZIP (11 KB) - IBIS Model
Modelo de simulación

SN65LVP17 with Gain Control GC tied to NC IBIS Model

SLLC236.ZIP (10 KB) - IBIS Model
Modelo de simulación

SN65LVP17 with Gain Control GC tied to VCC IBIS Model

SLLC237.ZIP (11 KB) - IBIS Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
WSON (DRF) 8 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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