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SN75ALS197

ACTIVO

Receptor de línea diferencial cuádruple

Detalles del producto

Protocols RS-422 Rating Catalog Operating temperature range (°C) 0 to 70
Protocols RS-422 Rating Catalog Operating temperature range (°C) 0 to 70
SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) SOP (NS) 16 79.56 mm² (10.2 mm × 7.8 mm) PDIP (N) 16 181.42 mm² (19.3 mm × 9.4 mm)
  • Meets or exceeds the requirements of ITU recommendations V.10, V.11, X.26, and X.27
  • Designed for multipoint bus transmission on long bus lines in noisy environments
  • Designed to operate Up to 20 Mbaud
  • 3-State outputs
  • Common-mode input voltage Range: − 7 V to 7 V
  • Input sensitivity: ±300 mV
  • Input hysteresis: 120 mV typical
  • High-input impedance: 12 kΩ minimum
  • Operates from single 5-V supply
  • Low supply-current requirement 35 mA maximum
  • Improved speed and power consumption compared to AM26LS32A
  • Meets or exceeds the requirements of ITU recommendations V.10, V.11, X.26, and X.27
  • Designed for multipoint bus transmission on long bus lines in noisy environments
  • Designed to operate Up to 20 Mbaud
  • 3-State outputs
  • Common-mode input voltage Range: − 7 V to 7 V
  • Input sensitivity: ±300 mV
  • Input hysteresis: 120 mV typical
  • High-input impedance: 12 kΩ minimum
  • Operates from single 5-V supply
  • Low supply-current requirement 35 mA maximum
  • Improved speed and power consumption compared to AM26LS32A

The SN75ALSI97 is a monolithic, quadruple line receiver with 3-state outputs designed using advanced, low-power, Schottky technology. This technology provides combined improvements in bar design, tooling production, and wafer fabrication. This, in turn, provides significantly lower power requirements and permits much higher data throughput than other designs. The device meets the specifications of ITU Recommendations V.10, V.11, X.26, and X.27. The 3-state outputs feature permits direct connection to a bus-organized system with a fail-safe design that makes sure the outputs is always high if the inputs are open.

The device is optimized for balanced, multipoint bus transmission at rates up to 20 megabits per second. The input features high-input impedance, input hysteresis for increased noise immunity, and an input sensitivity of ±300 mV over a common-mode input voltage range of −7 V to 7 V. The device also features active-high and active-low enable functions that are common to the four channels. The device is designed for optimum performance when used with the SN75ALS192 quadruple differential line driver.

The SN75ALS197 is characterized for operation from 0°C to 70°C.

The SN75ALSI97 is a monolithic, quadruple line receiver with 3-state outputs designed using advanced, low-power, Schottky technology. This technology provides combined improvements in bar design, tooling production, and wafer fabrication. This, in turn, provides significantly lower power requirements and permits much higher data throughput than other designs. The device meets the specifications of ITU Recommendations V.10, V.11, X.26, and X.27. The 3-state outputs feature permits direct connection to a bus-organized system with a fail-safe design that makes sure the outputs is always high if the inputs are open.

The device is optimized for balanced, multipoint bus transmission at rates up to 20 megabits per second. The input features high-input impedance, input hysteresis for increased noise immunity, and an input sensitivity of ±300 mV over a common-mode input voltage range of −7 V to 7 V. The device also features active-high and active-low enable functions that are common to the four channels. The device is designed for optimum performance when used with the SN75ALS192 quadruple differential line driver.

The SN75ALS197 is characterized for operation from 0°C to 70°C.

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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos SN75ALS197 Quadruple Differential Line Receiver datasheet (Rev. C) PDF | HTML 16/10/2023

Diseño y desarrollo

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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (D) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian
PDIP (N) 16 Ultra Librarian

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