The TMS470R1A256(2) devices are
members of the Texas Instruments TMS470R1x family of general-purpose 16/32-bit
reduced instruction set computer (RISC) microcontrollers. The A256
microcontroller offers high performance utilizing the high-speed ARM7TDMI
16/32-bit RISC central processing unit (CPU), resulting in a high instruction
throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit
RISC CPU views memory as a linear collection of bytes numbered upwards from
0. The TMS470R1A256 utilizes the big-endian format where the most
significant byte of a word is stored at the lowest numbered byte and the least
significant byte at the highest numbered byte.
High-end embedded control applications demand more
performance from their controllers while maintaining low costs. The A256 RISC
core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.
The A256 device contains the following:
- ARM7TDMI 16/32-Bit RISC
CPU
- TMS470R1x system module (SYS) with 470+
enhancements
- 256K-byte
flash
- 12K-byte SRAM
- Zero-pin phase-locked loop (ZPLL) clock
module
- Analog watchdog (AWD)
timer
- Real-time interrupt (RTI)
module
- Two serial peripheral interface (SPI)
modules
- Two serial communications interface
(SCI) modules
- Standard CAN controller
(SCC)
- Class II serial interface
(C2SIb)
- 10-bit multi-buffered
analog-to-digital converter (MibADC), 16-input
channels
- High-end timer (HET)
controlling 16 I/Os
- External clock prescale (ECP) module
- Up to 49 I/O pins and 1 input-only
pin
The functions performed by the 470+ system module (SYS)
include:
- Address decoding
- Memory protection
- Memory and peripherals bus
supervision
- Reset and abort exception management
- Prioritization for all
internal interrupt sources
- Device clock control
- Parallel signature
analysis (PSA)
This data sheet includes device-specific information such as
memory and peripheral select assignment, interrupt priority, and a device
memory map. For a more detailed functional description of the SYS module, see
the TMS470R1x System Module Reference
Guide (literature number SPNU189).
The A256 memory includes general-purpose SRAM supporting
single-cycle read/write accesses in byte, half-word, and word modes.
The flash memory on this device is a nonvolatile,
electrically erasable and programmable memory implemented with a 32-bit-wide
data bus interface. In pipeline mode, the flash operates with a system clock frequency of up
to 48 MHz. In normal mode, the flash operates with a system clock frequency of up to 24
MHz. For more detailed information on the flash, see the F05 flash section of
this data sheet and the TMS470R1x F05
Flash Reference Guide (literature number SPNU213).
The A256 device has six communication interfaces: two SPIs,
two SCIs, an SCC, and a C2SIb. The SPI provides a convenient method of serial
interaction for high-speed communications between similar shift-register type
devices. The SCI is a full-duplex, serial I/O interface intended for
asynchronous communication between the CPU and other peripherals using the
standard non-return-to-zero (NRZ) format. The SCC uses a serial, multimaster
communication protocol that efficiently supports distributed real-time control
with robust communication rates of up to 1 megabit per second (Mbps). The SCC
is ideal for applications operating in noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or
multiplexed wiring. The C2SIb allows the A256 to transmit and receive messages
on a class II network following an SAE J1850SAE
Standard J1850 Class B Data Communication Network Interface
standard. For more detailed functional information on the SPI, SCI, and SCC
peripherals, see the specific reference guides (literature numbers SPNU195,
SPNU196, and SPNU197, respectively). For more detailed functional information
on the C2SIb peripheral, see the TMS470R1x
Class II Serial Interface B (C2SIb) Reference Guide (literature
number SPNU214).
The HET is an advanced intelligent timer that provides
sophisticated timing functions for real-time applications. The timer is
software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The HET can be used for compare,
capture, or general-purpose I/O. It is especially well suited for applications
requiring multiple sensor information and drive actuators with complex and
accurate time pulses. For more detailed functional information on the HET, see
the TMS470R1x High-End Timer (HET)
Reference Guide (literature number SPNU199).
The A256 HET peripheral contains the XOR-share
feature. This feature allows two adjacent HET high-resolution channels to be
XORed together, making it possible to output smaller pulses than a standard
HET. For more detailed information on the HET XOR-share feature, see the
TMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).
The A256 device has a 10-bit-resolution sample-and-hold
MibADC. The MibADC channels can be converted individually or can be grouped by
software for sequential conversion sequences. There are three separate
groupings, two of which are triggerable by an external event. Each sequence can
be converted once when triggered or configured for continuous conversion mode.
For more detailed functional information on the MibADC, see the
TMS470R1x Multi-Buffered Analog-to-Digital
Converter (MibADC) Reference Guide (literature number
SPNU206).
The zero-pin phase-locked loop (ZPLL) clock module contains
a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a
prescaler (with prescale values of 1-8). The function of the ZPLL is to
multiply the external frequency reference to a higher frequency for internal
use. The ZPLL provides ACLK
to the system (SYS) module. The SYS module subsequently
provides the system clock (SYSCLK), real-time interrupt clock (RTICLK), CPU clock
(MCLK), and peripheral interface clock (ICLK) to all other A256 device
modules. For more detailed functional information on the ZPLL, see the
TMS470R1x Zero-Pin Phase Locked Loop
(ZPLL) Clock Module Reference Guide (literature number
SPNU212).
NOTE: ACLK should not be confused with the MibADC internal clock, ADCLK.
ACLK is the continuous system clock from an external resonator/crystal
reference.
The A256 device also has an external clock prescaler (ECP)
module that when enabled, outputs a continuous external clock (ECLK) on a
specified GIO pin. The ECLK frequency is a user-programmable ratio of the
peripheral interface clock (ICLK) frequency. For more detailed functional
information on the ECP, see the TMS470R1x
External Clock Prescaler (ECP) Reference Guide (literature number
SPNU202).
The TMS470R1A256(2) devices are
members of the Texas Instruments TMS470R1x family of general-purpose 16/32-bit
reduced instruction set computer (RISC) microcontrollers. The A256
microcontroller offers high performance utilizing the high-speed ARM7TDMI
16/32-bit RISC central processing unit (CPU), resulting in a high instruction
throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit
RISC CPU views memory as a linear collection of bytes numbered upwards from
0. The TMS470R1A256 utilizes the big-endian format where the most
significant byte of a word is stored at the lowest numbered byte and the least
significant byte at the highest numbered byte.
High-end embedded control applications demand more
performance from their controllers while maintaining low costs. The A256 RISC
core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.
The A256 device contains the following:
- ARM7TDMI 16/32-Bit RISC
CPU
- TMS470R1x system module (SYS) with 470+
enhancements
- 256K-byte
flash
- 12K-byte SRAM
- Zero-pin phase-locked loop (ZPLL) clock
module
- Analog watchdog (AWD)
timer
- Real-time interrupt (RTI)
module
- Two serial peripheral interface (SPI)
modules
- Two serial communications interface
(SCI) modules
- Standard CAN controller
(SCC)
- Class II serial interface
(C2SIb)
- 10-bit multi-buffered
analog-to-digital converter (MibADC), 16-input
channels
- High-end timer (HET)
controlling 16 I/Os
- External clock prescale (ECP) module
- Up to 49 I/O pins and 1 input-only
pin
The functions performed by the 470+ system module (SYS)
include:
- Address decoding
- Memory protection
- Memory and peripherals bus
supervision
- Reset and abort exception management
- Prioritization for all
internal interrupt sources
- Device clock control
- Parallel signature
analysis (PSA)
This data sheet includes device-specific information such as
memory and peripheral select assignment, interrupt priority, and a device
memory map. For a more detailed functional description of the SYS module, see
the TMS470R1x System Module Reference
Guide (literature number SPNU189).
The A256 memory includes general-purpose SRAM supporting
single-cycle read/write accesses in byte, half-word, and word modes.
The flash memory on this device is a nonvolatile,
electrically erasable and programmable memory implemented with a 32-bit-wide
data bus interface. In pipeline mode, the flash operates with a system clock frequency of up
to 48 MHz. In normal mode, the flash operates with a system clock frequency of up to 24
MHz. For more detailed information on the flash, see the F05 flash section of
this data sheet and the TMS470R1x F05
Flash Reference Guide (literature number SPNU213).
The A256 device has six communication interfaces: two SPIs,
two SCIs, an SCC, and a C2SIb. The SPI provides a convenient method of serial
interaction for high-speed communications between similar shift-register type
devices. The SCI is a full-duplex, serial I/O interface intended for
asynchronous communication between the CPU and other peripherals using the
standard non-return-to-zero (NRZ) format. The SCC uses a serial, multimaster
communication protocol that efficiently supports distributed real-time control
with robust communication rates of up to 1 megabit per second (Mbps). The SCC
is ideal for applications operating in noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or
multiplexed wiring. The C2SIb allows the A256 to transmit and receive messages
on a class II network following an SAE J1850SAE
Standard J1850 Class B Data Communication Network Interface
standard. For more detailed functional information on the SPI, SCI, and SCC
peripherals, see the specific reference guides (literature numbers SPNU195,
SPNU196, and SPNU197, respectively). For more detailed functional information
on the C2SIb peripheral, see the TMS470R1x
Class II Serial Interface B (C2SIb) Reference Guide (literature
number SPNU214).
The HET is an advanced intelligent timer that provides
sophisticated timing functions for real-time applications. The timer is
software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The HET can be used for compare,
capture, or general-purpose I/O. It is especially well suited for applications
requiring multiple sensor information and drive actuators with complex and
accurate time pulses. For more detailed functional information on the HET, see
the TMS470R1x High-End Timer (HET)
Reference Guide (literature number SPNU199).
The A256 HET peripheral contains the XOR-share
feature. This feature allows two adjacent HET high-resolution channels to be
XORed together, making it possible to output smaller pulses than a standard
HET. For more detailed information on the HET XOR-share feature, see the
TMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).
The A256 device has a 10-bit-resolution sample-and-hold
MibADC. The MibADC channels can be converted individually or can be grouped by
software for sequential conversion sequences. There are three separate
groupings, two of which are triggerable by an external event. Each sequence can
be converted once when triggered or configured for continuous conversion mode.
For more detailed functional information on the MibADC, see the
TMS470R1x Multi-Buffered Analog-to-Digital
Converter (MibADC) Reference Guide (literature number
SPNU206).
The zero-pin phase-locked loop (ZPLL) clock module contains
a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a
prescaler (with prescale values of 1-8). The function of the ZPLL is to
multiply the external frequency reference to a higher frequency for internal
use. The ZPLL provides ACLK
to the system (SYS) module. The SYS module subsequently
provides the system clock (SYSCLK), real-time interrupt clock (RTICLK), CPU clock
(MCLK), and peripheral interface clock (ICLK) to all other A256 device
modules. For more detailed functional information on the ZPLL, see the
TMS470R1x Zero-Pin Phase Locked Loop
(ZPLL) Clock Module Reference Guide (literature number
SPNU212).
NOTE: ACLK should not be confused with the MibADC internal clock, ADCLK.
ACLK is the continuous system clock from an external resonator/crystal
reference.
The A256 device also has an external clock prescaler (ECP)
module that when enabled, outputs a continuous external clock (ECLK) on a
specified GIO pin. The ECLK frequency is a user-programmable ratio of the
peripheral interface clock (ICLK) frequency. For more detailed functional
information on the ECP, see the TMS470R1x
External Clock Prescaler (ECP) Reference Guide (literature number
SPNU202).