The TPS7A52 is a low-noise (4.4 µVRMS), ultra-low dropout linear regulator (LDO) capable of sourcing 2 A with only 65 mV of maximum dropout. The device output voltage is adjustable from 0.8 V to 5.2 V using an external resistor divider.
The combination of low noise (4.4 µVRMS), high PSRR, and high output current capability makes the TPS7A52 an excellent choice to power noise-sensitive components such as those found in high-speed communications, video, medical, or test-and-measurement applications. The high performance of this device limits power-supply-generated phase noise and clock jitter, making this device ideal for powering high-performance serializer and deserializer (SerDes), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). Specifically, RF amplifiers benefit from the high performance and 5.2-V output capability of the device.
For digital loads [such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and digital signal processors (DSPs)] requiring low-input voltage, low-output (LILO) voltage operation, the exceptional accuracy (0.5% over load and temperature), remote sensing, excellent transient performance, and soft-start capabilities of the TPS7A52 provides optimal system performance.
As an adjustable voltage regulator, there is versatility in the design of the TPS7A52 that makes the device a component of choice for analog loads such as voltage-controlled oscillator (VCO), ADC, DAC, and imaging sensors and for digital loads such as SerDes, FPGAs, and DSPs.
Productos con especificaciones similares, ordenados por inventario disponible en TI.com.
| Documentación principal | Tipo | Título | Opciones de formato | Fecha |
|---|---|---|---|---|
| * | Data sheet | TPS7A52 2-A, High-Accuracy (0.5%), Low-Noise (4.4 µVRMS), LDO Voltage Regulator datasheet (Rev. A) | PDF | HTML | 23 mar 2020 |
| White paper | Demystifying LDO Turn-On (Start-Up) Time (Rev. B) | PDF | HTML | 10 mar 2026 | |
| White paper | Reduce System Noise Using Parallel LDOs | PDF | HTML | 03 nov 2025 | |
| White paper | Parallel LDO Architecture Design Using Ballast Resistors | PDF | HTML | 14 dic 2022 | |
| White paper | Comprehensive Analysis and Universal Equations for Parallel LDO's Using Ballast | PDF | HTML | 13 dic 2022 | |
| Technical article | Minimize noise and ripple with a low-noise buck converter | PDF | HTML | 21 oct 2020 |
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
El módulo de evaluación (EVM) TPS7A52 está diseñado para una configuración típica a fin de evaluar el funcionamiento y el rendimiento del dispositivo TPS7A52, que es un regulador de voltaje de caída baja (LDO), de 2-A, baja-VIN, baja-VOUT, y alta precisión.
La placa de circuito del EVM está (...)
The parallel low-dropout (LDO) calculator is a Microsoft® Excel®-based tool that provides worst-case analysis for parallel LDO regulators using ballast resistors. The tool helps the user identify the minimum number of parallel LDO regulators required and optimum ballast resistance for a (...)
| Encapsulado | Pines | Símbolos CAD, huellas y modelos 3D |
|---|---|---|
| VQFN-HR (RPS) | 12 | Ultra Librarian |
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