DS25BR110
- DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation
- Four Levels of Receive Equalization Reduce ISI Jitter
- On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space
- 7 kV ESD on LVDS I/O Pins Protects Adjoining Components
- Small 3 mm x 3 mm 8-WSON Space Saving Package
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The DS25BR110 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. A fully differential signal path ensures exceptional signal integrity and noise immunity.
The DS25BR110 features four levels of receive equalization (EQ), making it ideal for use as a receiver device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR120 features four levels of pre-emphasis for use as an optimized driver device, while the DS25BR100 features both pre-emphasis and equalization for use as an optimized repeater device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization.
Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. The differential inputs and outputs are internally terminated with a 100Ω resistor to lower device input and output return losses, reduce component count, and further minimize board space.
技術資料
| 上位の文書 | タイプ | タイトル | フォーマットオプション | 最新の英語版をダウンロード | 日付 | |
|---|---|---|---|---|---|---|
| * | データシート | DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization データシート (Rev. E) | 2013/04/14 | |||
| アプリケーション・ノート | Applications of Low-Voltage Differential Signaling (LVDS) in LED Walls | 2020/10/29 | ||||
| アプリケーション・ノート | Applications of Low-Voltage Differential Signaling (LVDS) in Ultrasound Scanners | 2019/06/29 | ||||
| アプリケーション・ノート | LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) | 2013/04/29 | ||||
| アプリケーション・ノート | AN-1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter (Rev. A) | 2013/04/26 | ||||
| ユーザー・ガイド | 3.125 Gbps LVDS Buffers with Pre-emphasis and Equalization User Guide | 2012/01/25 | ||||
| アプリケーション・ノート | データ伝送ラインにおけるシグナルパスの延長 | 英語版 | 2007/08/02 |
設計と開発
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DS25BR100EVK — 3.125Gbps LVDS シングル・チャネル・バッファ、送信プリエンファシスおよび受信イコライゼーション・ファミリ付
The DS25BR100EVK is an evaluation kit designed for demonstrating performance of the 3.125 Gbps LVDS Single Channel Buffers with Transmit Pre-Emphasis (PE) and Receive Equalization (EQ) family (DS25BR100, DS25BR110 and DS25BR120). The evaluation kit provides all three devices on a single board and (...)
| パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
|---|---|---|
| WSON (NGQ) | 8 | Ultra Librarian |
購入と品質
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