パッケージ情報
パッケージ | ピン数 TSSOP (DGG) | 48 |
動作温度範囲 (℃) -10 to 70 |
パッケージ数量 | キャリア 1,000 | LARGE T&R |
DS90CF564 の特徴
DS90CF564 に関する概要
The DS90CF563 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams.
A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of
the transmit clock 21 bits of input data are sampled and transmitted. The DS90CF564 receiver converts the LVDS data streams
back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing
and control data (FPLINE,
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.