パッケージ情報
| パッケージ | ピン数 WQFN (NKD) | 64 |
| 動作温度範囲 (℃) -40 to 105 |
| パッケージ数量 | キャリア 2,000 | LARGE T&R |
DS90UB940-Q1 の特徴
- AEC-Q100 qualified with the following results:
- Device temperature grade 2: –40°C to +105°C ambient operating temperature
- Supports pixel clock frequency up to 170 MHz for WUXGA (1920×1200) and 1080p60 resolutions With 24-Bit color depth
- 1-Lane or 2-Lane FPD-link III interface with deskew capability
- MIPI® D-PHY / CSI-2 transmitter
- CSI-2 output ports with selectable 2- or 4- lane operation, up to 1.3 Gbps each lane
- Video formats: RGB888/666/565, YUV422/420, RAW8/10/12
- Programmable virtual channel identifier
- Four high-speed GPIOs (up to 2 Mbps each)
- Adaptive receive equalization
- Compensates for channel insertion loss of up to –15.3 dB at 1.7 GHz
- Provides automatic temperature and cable aging compensation
- SPI control interfaces up to 3.3 Mbps
- I2C (Master/Slave) With 1-Mbps fast-mode plus
- Supports 7.1 multiple I2S (4 data) channels
DS90UB940-Q1 に関する概要
The DS90UB940-Q1 is a FPD-Link III deserializer which, together with the DS90UH949/947/929-Q1 serializers, converts 1-lane or 2-lane FPD-Link III streams into a MIPI® CSI-2 format. The deserializer can operate over cost-effective 50-Ω single-ended coaxial or 100-Ω differential shielded twisted-pair (STP) cables. It recovers the data from one or two FPD-Link III serial streams and translates it into a camera serial interface (CSI-2) format that can support video resolutions up to WUXGA and 1080p60 with 24-bit color depth.
The FPD-Link III interface supports video and audio data transmission and full duplex control, including I2C and SPI communication, over the same differential link. Consolidation of video data and control over two differential pairs decreases the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, and randomization. In backward compatible mode, the device supports up to WXGA and 720p resolutions with 24-bit color depth over a single differential link.
The device automatically senses the FPD-Link III channels and supplies a clock alignment and de-skew functionality without the need for any special training patterns. This ensures skew phase tolerance from mismatches in interconnect wires such as PCB trace routing, cable pair-to-pair length differences, and connector imbalances.