LMH0041
- 5-Bit LVDS Interface
- No External VCO or Clock Required
- Reclocked Serial Loopthrough With Cable Driver
- Powerdown Mode
- 3.3V SMBus Configuration Interface
- Small 48-Pin WQFN Package
- Industrial Temperature range: -40°C to +85°C
Key Specifications
- Output compliant with SMPTE 259M-C, SMPTE 292M, SMPTE 424M and DVB-ASI
- Typical power dissipation: 590 mW (loopthrough disabled, 3G datarate)
- 0.6 UI Minimum Input Jitter Tolerance
All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments.
The LMH0341/0041/0071/0051 SDI Deserializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. When paired with a host FPGA the LMH0341 automatically detects the incoming data rate and decodes the raw 5-bit data words compliant to any of the following standards: DVB-ASI, SMPTE 259M, SMPTE 292M, or SMPTE 424M. See for details on which Standards are supported per device.
The interface between the LMH0341 and the host FPGA consists of a 5-bit wide LVDS bus, an LVDS clock and an SMBus interface. No external VCOs or clocks are required. The LMH0341 CDR detects the frequency from the incoming data stream, generates a clean clock and transmits both clock and data to the host FPGA. The LMH0341, LMH0041 and LMH0071 include a serial reclocked loopthrough with integrated SMPTE compliant cable driver. Refer to for a complete listing of single channel deserializers offered in this family.
The FPGA-Attach SER/DES product family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The product is packaged in a physically small 48 pin WQFN package.
技術資料
| 上位の文書 | タイプ | タイトル | フォーマットオプション | 最新の英語版をダウンロード | 日付 | |
|---|---|---|---|---|---|---|
| * | データシート | LMH0341/041/071/051 3Gbps, HD, SD, DVB-ASI SDI Deserializr w/Loopthru & LVDS I/F データシート (Rev. Q) | 2013/04/16 | |||
| セレクション・ガイド | Broadcast and Professional Video Interface Solutions (Rev. E) | PDF | HTML | 2017/04/05 | |||
| アプリケーション・ノート | AN-2145 Power Considerations for SDI Products (Rev. B) | 2013/04/26 | ||||
| アプリケーション・ノート | AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) | 2013/04/26 | ||||
| アプリケーション・ノート | AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) | 2013/04/26 | ||||
| アプリケーション・ノート | AN-1988 LMH0340 / LMH0341 SerDes Family LVDS Timing Overview (Rev. A) | 2013/04/26 | ||||
| アプリケーション・ノート | High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems | 2009/11/12 | ||||
| アプリケーション・ノート | 非圧縮の1080p60ビデオをサポートする3Gbps SDIコネクティビティ･ソリューション | 英語版 | 2008/03/18 |
設計と開発
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SDXILIP — Xilinx Spartan サンプル コード
We have developed a family of serializers and deserializers intended to support the serial digital interface (SDI) standards of the Society of Motion Picture and Television Engineers (SMPTE). These devices connect to a host FPGA through a moderate speed, moderate width (600 Mbps, 5 bits wide) (...)
| パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |