SCAN92LV090
- IEEE 1149.1 (JTAG) Compliant
- Bus LVDS Signaling
- Low Power CMOS Design
- High Signaling Rate Capability (Above 100 Mbps)
- 0.1V to 2.3V Common Mode Range for VID = 200mV
- ±100 mV Receiver Sensitivity
- Supports Open and Terminated Failsafe on Port Pins
- 3.3V Operation
- Glitch Free Power Up/Down (Driver & Receiver Disabled)
- Light Bus Loading (5 pF Typical) per Bus LVDS Load
- Designed for Double Termination Applications
- Balanced Output Impedance
- Product Offered in 64 Pin LQFP Package and NFBGA Package
- High Impedance Bus Pins on Power Off (VCC = 0V)
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The SCAN92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector.
The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of ±1V.
The receiver threshold is less than ±100 mV over a ±1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels.
This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and the optional Test Reset (TRST).
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技術資料
| 上位の文書 | タイプ | タイトル | フォーマットオプション | 最新の英語版をダウンロード | 日付 | |
|---|---|---|---|---|---|---|
| * | データシート | SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN データシート (Rev. I) | 2013/04/12 |
設計と開発
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| パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
|---|---|---|
| NFBGA (NZC) | 64 | Ultra Librarian |
| LQFP (PM) | 64 | Ultra Librarian |
購入と品質
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