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SN65LVDS349

アクティブ

クワッド高速差動レシーバ

製品詳細

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Signaling rate (Mbps) 560 Input signal CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Signaling rate (Mbps) 560 Input signal CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm)
  • Meets or Exceeds the Requirements of ANSI
    TIA/EIA-644A Standard
  • Single-Channel Signaling Rates up to
    560 Mbps
  • –4 V to 5 V Common-Mode Input Voltage
    Range
  • Flow-Through Architecture
  • SN65LVDS349 Provides a Wide Common-Mode Range Replacement
    for the SN65LVDS048A or the DS90LV048A
  • APPLICATIONS
    • Logic Level Translator
    • Point-to-Point Baseband Data Transmission
      Over 100- Media
    • ECL/PECL-to-LVTTL Conversion
    • Wireless Base Stations
    • Central Office or PABX Switches

  • Meets or Exceeds the Requirements of ANSI
    TIA/EIA-644A Standard
  • Single-Channel Signaling Rates up to
    560 Mbps
  • –4 V to 5 V Common-Mode Input Voltage
    Range
  • Flow-Through Architecture
  • SN65LVDS349 Provides a Wide Common-Mode Range Replacement
    for the SN65LVDS048A or the DS90LV048A
  • APPLICATIONS
    • Logic Level Translator
    • Point-to-Point Baseband Data Transmission
      Over 100- Media
    • ECL/PECL-to-LVTTL Conversion
    • Wireless Base Stations
    • Central Office or PABX Switches

The SN65LVDS349 is a high-speed, quadruple differential receiver with a wide common-mode input voltage range. This allows receipt of TIA/EIA-644 signals with up to 3-V of ground noise or a variety of differential and single-ended logic levels. The ’349 is in a 16-pin package to match the industry-standard footprint of the DS90LV048. The ’349 offers a flow-through architecture with all inputs on one side and outputs on the other to ease board layout and reduce crosstalk between receivers.

The LVDS349 provides 3x the standard’s minimum common-mode noise voltage tolerance. The –4 V to 5 V common-mode range allows usage in harsh operating environments or accepts LVPECL, PECL, LVECL, ECL, CMOS, and LVCMOS levels without level shifting circuitry. See the Application Information Section for more details on the ECL/PECL to LVDS interface.

Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input-voltage hysteresis to improve noise rejection. The differential input thresholds are still no more than ±50 mV over the full input common-mode voltage range.

The receiver inputs can withstand ±15 kV human-body model (HBM), with respect to ground, without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.

The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS349 is characterized for operation from –40°C to 85°C.

The SN65LVDS349 is a high-speed, quadruple differential receiver with a wide common-mode input voltage range. This allows receipt of TIA/EIA-644 signals with up to 3-V of ground noise or a variety of differential and single-ended logic levels. The ’349 is in a 16-pin package to match the industry-standard footprint of the DS90LV048. The ’349 offers a flow-through architecture with all inputs on one side and outputs on the other to ease board layout and reduce crosstalk between receivers.

The LVDS349 provides 3x the standard’s minimum common-mode noise voltage tolerance. The –4 V to 5 V common-mode range allows usage in harsh operating environments or accepts LVPECL, PECL, LVECL, ECL, CMOS, and LVCMOS levels without level shifting circuitry. See the Application Information Section for more details on the ECL/PECL to LVDS interface.

Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input-voltage hysteresis to improve noise rejection. The differential input thresholds are still no more than ±50 mV over the full input common-mode voltage range.

The receiver inputs can withstand ±15 kV human-body model (HBM), with respect to ground, without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.

The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS349 is characterized for operation from –40°C to 85°C.

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技術資料

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上位の文書 タイプ タイトル フォーマットオプション 最新の英語版をダウンロード 日付
* データシート Quad High-Speed Differential Receiver データシート 2010/09/14
アプリケーション概要 LVDS to Improve EMC in Motor Drives 2018/09/27
アプリケーション概要 How Far, How Fast Can You Operate LVDS Drivers and Receivers? 2018/08/03
アプリケーション概要 How to Terminate LVDS Connections with DC and AC Coupling 2018/05/16
アプリケーション・ノート SN65LVDS348 vs SN65LVDS349 2010/10/05
アプリケーション・ノート LVDS技術の概要 英語版 1998/10/05

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TSSOP (PW) 16 Ultra Librarian

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