제품 상세 정보

Function Zero-delay Additive RMS jitter (typ) (fs) 200 Output frequency (max) (MHz) 125 Number of outputs 9 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 200 Operating temperature range (°C) 0 to 70 Rating Catalog Output type TTL Input type TTL
Function Zero-delay Additive RMS jitter (typ) (fs) 200 Output frequency (max) (MHz) 125 Number of outputs 9 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 200 Operating temperature range (°C) 0 to 70 Rating Catalog Output type TTL Input type TTL
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • Use CDCVF2509A as a Replacement for this Device
  • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
  • Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
  • Separate Output Enable for Each Output Bank
  • External Feedback (FBIN) Pin Is Used to Synchronize the Outputs to the Clock Input
  • No External RC Network Required
  • Operates at 3.3-V VCC
  • Packaged in Plastic 24-Pin Thin Shrink Small-Outline Package
  • Use CDCVF2509A as a Replacement for this Device
  • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
  • Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
  • Separate Output Enable for Each Output Bank
  • External Feedback (FBIN) Pin Is Used to Synchronize the Outputs to the Clock Input
  • No External RC Network Required
  • Operates at 3.3-V VCC
  • Packaged in Plastic 24-Pin Thin Shrink Small-Outline Package

The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3-V VCC and is designed to drive up to five clock loads per output.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.

The CDC509 is characterized for operation from 0°C to 70°C.

The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3-V VCC and is designed to drive up to five clock loads per output.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.

The CDC509 is characterized for operation from 0°C to 70°C.

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* Data sheet CDC509: 3.3-V Phase-Lock Loop Clock Driver datasheet (Rev. C) 2004/12/02
Application note High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A) 1998/09/23

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시뮬레이션 모델

CDC509 IBIS Model

SCAC013.ZIP (2 KB) - IBIS Model
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