PLLATINUMSIM-SW — PLLatinum Sim Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
The CDCLVP1102 is a highly versatile, low additive jitter buffer that can generate two copies of LVPECL clock outputs from one LVPECL, LVDS, or LVCMOS input for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1102 clock buffer distributes a single clock input (IN) to two pairs of differential LVPECL clock outputs (OUT0, OUT1) with minimum skew for clock distribution. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1102 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP1102 is characterized for operation from 40°C to 85°C and is available in a QFN-16, 3-mm × 3-mm package.
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer datasheet (Rev. D) | PDF | HTML | 2015/12/11 |
| EVM User's guide | CDCLVP1102EVM User's Guide | 2009/07/09 |
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The CDCLVP1102 is a high-performance, low additive phase noise clock buffer. It has a single universal input buffer that supports either single-ended or differential clock inputs, and feeds to two LVPECL outputs. The device also features on-chip bias generators that can provide the LVPECL (...)
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| VQFN (RGT) | 16 | Ultra Librarian |
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.
PLLatinum Sim User's Guide
PLLatinum Sim software manifest
PLLatinum Sim 1.6.9 includes the ability to manually specify points on a phase noise curve (for VCOs or other devices that do not fit the standard three-point model), and as a result the phase noise estimation for many devices which use a BAW VCO is greatly improved. Also includes a bugfix for cascading noise inputs.