LMK04828-EP

활성

온도 범위 55~105°C의 초저잡음 JESD204B 호환 클록 지터 클리너

지금 주문하기

데이터 시트

document-pdfAcrobat LMK04828-EP Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner datasheet (영어) PDF | HTML

LMK04828-EP

활성

데이터 시트

지금 주문하기

제품 상세 정보

Number of input channels

3

Number of outputs

14

RMS jitter (fs)

88

Features

JESD204B

Output frequency (min) (MHz)

0.001

Output frequency (max) (MHz)

3200

Output type

LVDS, LVPECL

Input type

LVCMOS, LVDS, LVPECL

Operating temperature range (°C)

-55 to 105

Number of input channels

3

Number of outputs

14

RMS jitter (fs)

88

Features

JESD204B

Output frequency (min) (MHz)

0.001

Output frequency (max) (MHz)

3200

Output type

LVDS, LVPECL

Input type

LVCMOS, LVDS, LVPECL

Operating temperature range (°C)

-55 to 105

WQFN (NKD)

64

81 mm² (9 mm × 9 mm)

EP Features
- Gold Bondwires
- Temperature Range: –55 to +105 °C
- Lead Finish SnPb
Maximum Distribution Frequency: 3.2 GHz
JESD204B Support
Ultra-Low RMS Jitter
- 88-fs RMS Jitter (12 kHz to 20 MHz)
- 91-fs RMS Jitter (100 Hz to 20 MHz)
- –162.5 dBc/Hz Noise Floor at 245.76 MHz
Up to 14 Differential Device Clocks From PLL2
- Up to 7 SYSREF Clocks
- Maximum Clock Output Frequency 3.2 GHz
- LVPECL, LVDS, HSDS, LCPECL Programmable Outputs From PLL2
Up to 1 Buffered VCXO/Crystal Output From PLL1
- LVPECL, LVDS, 2xLVCMOS Programmable
Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
Dual Loop PLLatinum™ PLL Architecture
PLL1
- Up to 3 Redundant Input Clocks
  - Automatic and Manual Switchover Modes
  - Hitless Switching and LOS
- Integrated Low-Noise Crystal Oscillator Circuit
- Holdover Mode When Input Clocks are Lost
PLL2
- Normalized [1 Hz] PLL Noise Floor of
  –227 dBc/Hz
- Phase Detector Rate up to 155 MHz
- OSCin Frequency-Doubler
- Two Integrated Low-Noise VCOs
50% Duty Cycle Output Divides, 1 to 32
(Even and Odd)
Precision Digital Delay, Dynamically Adjustable
25-ps Step Analog Delay
3.15-V to 3.45-V Operation
Package: 64-Pin WQFN (9.0 mm × 9.0 mm × 0.8 mm)

EP Features
- Gold Bondwires
- Temperature Range: –55 to +105 °C
- Lead Finish SnPb
Maximum Distribution Frequency: 3.2 GHz
JESD204B Support
Ultra-Low RMS Jitter
- 88-fs RMS Jitter (12 kHz to 20 MHz)
- 91-fs RMS Jitter (100 Hz to 20 MHz)
- –162.5 dBc/Hz Noise Floor at 245.76 MHz
Up to 14 Differential Device Clocks From PLL2
- Up to 7 SYSREF Clocks
- Maximum Clock Output Frequency 3.2 GHz
- LVPECL, LVDS, HSDS, LCPECL Programmable Outputs From PLL2
Up to 1 Buffered VCXO/Crystal Output From PLL1
- LVPECL, LVDS, 2xLVCMOS Programmable
Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
Dual Loop PLLatinum™ PLL Architecture
PLL1
- Up to 3 Redundant Input Clocks
  - Automatic and Manual Switchover Modes
  - Hitless Switching and LOS
- Integrated Low-Noise Crystal Oscillator Circuit
- Holdover Mode When Input Clocks are Lost
PLL2
- Normalized [1 Hz] PLL Noise Floor of
  –227 dBc/Hz
- Phase Detector Rate up to 155 MHz
- OSCin Frequency-Doubler
- Two Integrated Low-Noise VCOs
50% Duty Cycle Output Divides, 1 to 32
(Even and Odd)
Precision Digital Delay, Dynamically Adjustable
25-ps Step Analog Delay
3.15-V to 3.45-V Operation
Package: 64-Pin WQFN (9.0 mm × 9.0 mm × 0.8 mm)

The LMK04828-EP device is the industry’s highest performance clock conditioner with JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The high performance combined with features like the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay make the LMK04828-EP ideal for providing flexible high-performance clocking trees.

The LMK04828-EP device is the industry’s highest performance clock conditioner with JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The high performance combined with features like the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay make the LMK04828-EP ideal for providing flexible high-performance clocking trees.

filter

기타 클록 지터 클리너 찾기

다운로드 스크립트와 함께 비디오 보기 비디오

관심 가지실만한 유사 제품

open-in-new

대안 비교

비교 대상 장치와 유사한 기능.

LMK04832-SEP

활성

Radiation-tolerant, 30krad, ultra-low-noise, 3.2GHz 15-output JESD204C clock jitter cleaner 3.2-GHz jitter cleaner with JESD204C support, 30-krad TID, and 43-MeV-cm2/mg for space missions

LMK04368-EP

활성

향상된 제품 초저잡음 3.2GHz JESD204C 지터 클리너 Up to 125 C vs 105 C temperature option.

기술 자료

검색된 결과가 없습니다. 검색어를 지우고 다시 시도하세요.

2개 모두 보기

상위 문서	유형	직함	형식 옵션	최신 영어 버전 다운로드	날짜
*	데이터 시트	LMK04828-EP Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner datasheet	PDF \| HTML		2017. 4. 3
	애플리케이션 노트	Multi-Clock Synchronization			2019. 12. 30

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

지원 소프트웨어

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

텍사스 인스트루먼트 클록 및 신시사이저(TICS) Pro 소프트웨어는 다음 접두사를 사용하여 제품 번호의 평가 모듈(EVM)을 프로그래밍하는 데 사용됩니다. CDC, LMK 및 LMX. 이러한 제품에는 위상 동기 루프 및 전압 제어 오실레이터(PLL+VCO), 신시사이저 및 클로킹 디바이스가 포함되어 있습니다.

지원되는 제품 및 하드웨어

다운로드 옵션

시뮬레이션 모델