LMK1D1208I

활성

I²C를 지원하는 8채널 출력 1.8V, 2.5V 및 3.3V LVDS 버퍼

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document-pdfAcrobat LMK1D1208I I2C-Configurable, Low-Additive Jitter LVDS Buffer datasheet (Rev. A) (영어) PDF | HTML

LMK1D1208I

활성

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제품 상세 정보

Number of outputs

8

Additive RMS jitter (typ) (fs)

50

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LVDS

Input type

HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL

Number of outputs

8

Additive RMS jitter (typ) (fs)

50

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LVDS

Input type

HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL

VQFN (RHA)

40

36 mm² (6 mm × 6 mm)

High-performance LVDS clock buffer family with 2 inputs and 8 outputs
Output frequency up to 2 GHz
Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5%
Device configurability through I 2C programming
- Individual input and output enable/disable
- Individual output amplitude select (standard or boosted)
- Bank input multiplexer
Four programmable I 2C addresses through IDX pins
Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz
- Very low phase noise floor: -164 dBc/Hz (typical)
Very low propagation delay: < 575 ps maximum
Output skew: 20 ps maximum
Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML
Fail-safe inputs
LVDS reference voltage, V AC_REF, available for capacitive coupled inputs
Industrial temperature range: –40°C to 105°C
Packages available
- 6-mm × 6-mm, 40-Pin VQFN (RHA)

High-performance LVDS clock buffer family with 2 inputs and 8 outputs
Output frequency up to 2 GHz
Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5%
Device configurability through I 2C programming
- Individual input and output enable/disable
- Individual output amplitude select (standard or boosted)
- Bank input multiplexer
Four programmable I 2C addresses through IDX pins
Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz
- Very low phase noise floor: -164 dBc/Hz (typical)
Very low propagation delay: < 575 ps maximum
Output skew: 20 ps maximum
Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML
Fail-safe inputs
LVDS reference voltage, V AC_REF, available for capacitive coupled inputs
Industrial temperature range: –40°C to 105°C
Packages available
- 6-mm × 6-mm, 40-Pin VQFN (RHA)

The LMK1D1208I is an I 2C-programmable LVDS clock buffer. The device has two inputs and eight pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The inputs can either be LVDS, LVPECL, LVCMOS, HCSL, or CML.

The LMK1D1208I is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin.

I 2C programming enables this device to be configured as a single bank buffer (one of the two inputs is distributed to eight output pairs) or as a dual bank buffer (each input is distributed to four outputs pairs). Each output can be configured to have either a standard (350 mV) or boosted (500 mV) swing. This device also incorporates individual output channel enable or disable through I 2C programming. The LMK1D1208I has fail-safe inputs that prevent oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

The LMK1D1208I is an I 2C-programmable LVDS clock buffer. The device has two inputs and eight pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The inputs can either be LVDS, LVPECL, LVCMOS, HCSL, or CML.

The LMK1D1208I is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin.

I 2C programming enables this device to be configured as a single bank buffer (one of the two inputs is distributed to eight output pairs) or as a dual bank buffer (each input is distributed to four outputs pairs). Each output can be configured to have either a standard (350 mV) or boosted (500 mV) swing. This device also incorporates individual output channel enable or disable through I 2C programming. The LMK1D1208I has fail-safe inputs that prevent oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

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상위 문서	유형	직함	형식 옵션	최신 영어 버전 다운로드	날짜
*	데이터 시트	LMK1D1208I I2C-Configurable, Low-Additive Jitter LVDS Buffer datasheet (Rev. A)	PDF \| HTML		2023. 6. 14

설계 및 개발

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평가 보드

LMK1D1208IEVM — I²C를 지원하는 8채널 출력, 1.8V, 2.5V 및 3.3V LVDS 버퍼용 LMK1D1208I 평가 모듈

LMK1D1208I 평가 모듈(EVM)은 LMK1D1208I의 전기적 성능을 시연할 수 있도록 설계했습니다. LMK1D1208I는 I2C 구성 가능한 고성능 저가산 지터 LVDS 클록 버퍼로, 차동 입력 2개와 LVDS 출력이 8개 있습니다. LMK1D1208IEVM에는 최고의 성능을 위해 50Ω SMA 커넥터와 임피던스 제어 50Ω 마이크로스트립 전송선이 내장되어 있습니다.

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