제품 상세 정보

Technology family GTL Applications MDIO, PMBus, SDIO, SMBus Rating Catalog Operating temperature range (°C) -40 to 85
Technology family GTL Applications MDIO, PMBus, SDIO, SMBus Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • Provides Bidirectional Voltage Translation With No Direction Control Required
  • Allows Voltage Level Translation From 1 V up to 5 V
  • Provides Direct Interface With GTL, GTL+, LVTTL/TTL, and 5-V CMOS Levels
  • Low On-State Resistance Between Input and Output Pins (Sn/Dn)
  • Supports Hot Insertion
  • No Power Supply Required — Will Not Latch Up
  • 5-V-Tolerant Inputs
  • Low Standby Current
  • Flow-Through Pinout for Ease of Printed Circuit Board Trace Routing
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-4)
    • 1000-V Charged-Device Model (C101)
  • APPLICATIONS
    • Bidirectional or Unidirectional Applications Requiring Voltage-Level Translation From Any Voltage (1 V to 5 V) to Any Voltage (1 V to 5 V)
    • Low Voltage Processor I2C Port Translation to 3.3-V and/or 5-V I2C Bus Signal Levels
    • GTL/GTL+ Translation to LVTTL/TTL Signal Levels

  • Provides Bidirectional Voltage Translation With No Direction Control Required
  • Allows Voltage Level Translation From 1 V up to 5 V
  • Provides Direct Interface With GTL, GTL+, LVTTL/TTL, and 5-V CMOS Levels
  • Low On-State Resistance Between Input and Output Pins (Sn/Dn)
  • Supports Hot Insertion
  • No Power Supply Required — Will Not Latch Up
  • 5-V-Tolerant Inputs
  • Low Standby Current
  • Flow-Through Pinout for Ease of Printed Circuit Board Trace Routing
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-4)
    • 1000-V Charged-Device Model (C101)
  • APPLICATIONS
    • Bidirectional or Unidirectional Applications Requiring Voltage-Level Translation From Any Voltage (1 V to 5 V) to Any Voltage (1 V to 5 V)
    • Low Voltage Processor I2C Port Translation to 3.3-V and/or 5-V I2C Bus Signal Levels
    • GTL/GTL+ Translation to LVTTL/TTL Signal Levels

The GTL2010 provides ten NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The low ON-state resistance of the switch allows connections to be made with minimal propagation delay. With no direction control pin required, the device allows bidirectional voltage translations any voltage (1 V to 5 V) to any voltage (1 V to 5 V).

When the Sn or Dn port is LOW, the clamp is in the ON state and a low-resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VCC by the pullup resistors.

All transistors in the GTL2010 have the same electrical characteristics, and there is minimal deviation from one output to another in voltage or propagation delay. This offers superior matching over discrete transistor voltage-translation solutions where the fabrication of the transistors is not symmetrical. With all transistors being identical, the reference transistor (SREF/DREF) can be located on any of the other ten matched Sn/Dn transistors, allowing for easier board layout. The translator transistors with integrated ESD circuitry provides excellent ESD protection.

The GTL2010 provides ten NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The low ON-state resistance of the switch allows connections to be made with minimal propagation delay. With no direction control pin required, the device allows bidirectional voltage translations any voltage (1 V to 5 V) to any voltage (1 V to 5 V).

When the Sn or Dn port is LOW, the clamp is in the ON state and a low-resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VCC by the pullup resistors.

All transistors in the GTL2010 have the same electrical characteristics, and there is minimal deviation from one output to another in voltage or propagation delay. This offers superior matching over discrete transistor voltage-translation solutions where the fabrication of the transistors is not symmetrical. With all transistors being identical, the reference transistor (SREF/DREF) can be located on any of the other ten matched Sn/Dn transistors, allowing for easier board layout. The translator transistors with integrated ESD circuitry provides excellent ESD protection.

다운로드

관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 유사한 기능
LSF0108 활성 8진 양방향 멀티 전압 레벨 트랜스레이터 High speed and wider temperature range

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
1개 모두 보기
유형 직함 날짜
* Data sheet GTL2010 datasheet 2006/02/16

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​