AM4377
- Highlights
- Sitara™
ARM®
Cortex®-A9 32-Bit RISC
Processor With Processing Speed up to 1000 MHz
- NEON™ SIMD Coprocessor and Vector Floating Point (VFPv3) Coprocessor
- 32KB of Both L1 Instruction and Data Cache
- 256KB of L2 Cache or L3 RAM
- 32-Bit LPDDR2, DDR3, and DDR3L Support
- General-Purpose Memory Support (NAND, NOR, SRAM) Supporting up to 16-Bit ECC
- SGX530 Graphics Engine
- Display Subsystem
- Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
- Real-Time Clock (RTC)
- Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY
- 10, 100, and 1000 Ethernet Switch Supporting up to Two Ports
- Serial Interfaces:
- Two Controller Area Network (CAN) Ports
- Six UARTs, Two McASPs, Five McSPIs, Three I2C Ports, One QSPI, and One HDQ or 1-Wire
- Security
- Crypto Hardware Accelerators (AES, SHA, RNG, DES, and 3DES)
- Secure Boot (Avaliable Only on AM437x High-Security [AM437xHS] Devices)
- Two 12-Bit Successive Approximation Register (SAR) ADCs
- Up to Three 32-Bit Enhanced Capture (eCAP) Modules
- Up to Three Enhanced Quadrature Encoder Pulse (eQEP) Modules
- Up to Six Enhanced High-Resolution PWM (eHRPWM) Modules
- Sitara™
ARM®
Cortex®-A9 32-Bit RISC
Processor With Processing Speed up to 1000 MHz
- MPU Subsystem
- ARM Cortex-A9 32-Bit RISC Microprocessor With Processing Speed up to 1000 MHz
- 32KB of Both L1 Instruction and Data Cache
- 256KB of L2 Cache (Option to Configure as L3 RAM)
- 256KB of On-Chip Boot ROM
- 64KB of On-Chip RAM
- Secure Control Module (SCM) (Avaliable Only on AM437xHS Devices)
- Emulation and Debug
- JTAG
- Embedded Trace Buffer
- Interrupt Controller
- On-Chip Memory (Shared L3 RAM)
- 256KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
- Accessible to All Masters
- Supports Retention for Fast Wakeup
- Up to 512KB of Total Internal RAM
(256KB of ARM Memory Configured as L3 RAM + 256KB of OCMC RAM)
- External Memory Interfaces (EMIFs)
- DDR Controllers:
- LPDDR2: 266-MHz Clock (LPDDR2-533 Data Rate)
- DDR3 and DDR3L: 400-MHz Clock (DDR-800 Data Rate)
- 32-Bit Data Bus
- 2GB of Total Addressable Space
- Supports One x32, Two x16, or Four x8 Memory Device Configurations
- DDR Controllers:
- General-Purpose Memory Controller (GPMC)
- Flexible 8- and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, and SRAM)
- Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
- Uses Hamming Code to Support 1-Bit ECC
- Error Locator Module (ELM)
- Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
- Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms
- Programmable Real-Time Unit Subsystem and Industrial
Communication Subsystem (PRU-ICSS)
- Supports Protocols such as EtherCAT®, PROFIBUS®, PROFINET®, and EtherNet/IP™, EnDat 2.2, and More
- Two Programmable Real-Time Units (PRUs) Subsystems With Two PRU Cores
Each
- Each Core is a 32-Bit Load and Store RISC Processor Capable of Running at 200 MHz
- 12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Instruction RAM With Single-Error Detection (Parity)
- 8KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Data RAM With Single-Error Detection (Parity)
- Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
- Enhanced GPIO Module Provides Shift-In and Shift-Out Support and Parallel Latch on External Signal
- 12KB (PRU-ICSS1 Only) of Shared RAM With Single-Error Detection (Parity)
- Three 120-Byte Register Banks Accessible by Each PRU
- Interrupt Controller Module (INTC) for Handling System Input Events
- Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
- Peripherals Inside the PRU-ICSS
- One UART Port With Flow Control Pins, Supports up to 12 Mbps
- One eCAP Module
- Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
- One MDIO Port
- Industrial Communication is Supported by Two PRU-ICSS Subsystems
- Power, Reset, and Clock Management (PRCM)
Module
- Controls the Entry and Exit of Deep-Sleep Modes
- Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
- Clocks
- Integrated High-Frequency Oscillator Used to Generate a Reference Clock (19.2, 24, 25, and 26 MHz) for Various System and Peripheral Clocks
- Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
- Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB, and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], and LCD Pixel Clock)
- Power
- Two Nonswitchable Power Domains (RTC and Wake-Up Logic [WAKE-UP])
- Three Switchable Power Domains (MPU Subsystem, SGX530 [GFX], Peripherals and Infrastructure [PER])
- Dynamic Voltage Frequency Scaling (DVFS)
- Real-Time Clock (RTC)
- Real-Time Date (Day, Month, Year, and Day of Week) and Time (Hours, Minutes, and Seconds) Information
- Internal 32.768-kHz Oscillator, RTC Logic, and 1.1-V Internal LDO
- Independent Power-On-Reset (RTC_PWRONRSTn) Input
- Dedicated Input Pin (RTC_WAKEUP) for External Wake Events
- Programmable Alarm Can Generate Internal Interrupts to the PRCM for Wakeup or Cortex-A9 for Event Notification
- Programmable Alarm Can Be Used With External Output (RTC_PMIC_EN) to Enable the Power-Management IC to Restore Non-RTC Power Domains
- Peripherals
- Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY
- Up to Two Industrial Gigabit Ethernet MACs
(10, 100, and 1000 Mbps)- Integrated Switch
- Each MAC Supports MII, RMII, and RGMII and MDIO Interfaces
- Ethernet MACs and Switch Can Operate Independent of Other Functions
- IEEE 1588v2 Precision Time Protocol (PTP)
- Up to Two CAN
Ports
- Supports CAN Version 2 Parts A and B
- Up to Two Multichannel Audio Serial Ports
(McASPs)
- Transmit and Receive Clocks up to 50 MHz
- Up to Four Serial Data Pins Per McASP Port With Independent TX and RX Clocks
- Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
- Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
- FIFO Buffers for Transmit and Receive (256 Bytes)
- Up to Six UARTs
- All UARTs Support IrDA and CIR Modes
- All UARTs Support RTS and CTS Flow Control
- UART1 Supports Full Modem Control
- Up to Five Master and Slave McSPIs
- McSPI0–McSPI2 Support up to Four Chip Selects
- McSPI3 and McSPI4 Support up to Two Chip Selects
- Up to 48 MHz
- One Quad-SPI
- Supports eXecute In Place (XIP) from Serial NOR FLASH
- One Dallas 1-Wire® and HDQ Serial Interface
- Up to Three MMC, SD, and SDIO Ports
- 1-, 4-, and 8-Bit MMC, SD, and SDIO Modes
- 1.8- or 3.3-V Operation on All Ports
- Up to 48-MHz Clock
- Supports Card Detect and Write Protect
- Complies With MMC4.3 and SD and SDIO 2.0 Specifications
- Up to Three I2C
Master and Slave Interfaces
- Standard Mode (up to 100 kHz)
- Fast Mode (up to 400 kHz)
- Up to Six Banks of General-Purpose I/O (GPIO)
- 32 GPIOs per Bank (Multiplexed With Other Functional Pins)
- GPIOs Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
- Up to Three External DMA Event Inputs That Can Also be Used as Interrupt Inputs
- Twelve 32-Bit General-Purpose Timers
- DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
- DMTIMER4–DMTIMER7 are Pinned Out
- One Public Watchdog Timer
- One Free-Running, High-Resolution 32-kHz Counter (synctimer32K)
- One Secure Watchdog Timer (Avaliable Only on AM437xHS Devices)
- SGX530 3D Graphics Engine
- Tile-Based Architecture Delivering up to 20M Poly/sec
- Universal Scalable Shader Engine is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality
- Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0
- Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0
- Fine-Grained Task Switching, Load Balancing, and Power Management
- Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction
- Programmable High-Quality Image Anti-Aliasing
- Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
- Display Subsystem
- Display Modes
- Programmable Pixel Memory Formats (Palletized: 1-, 2-, 4-, and 8-Bits Per Pixel; RGB 16- and 24-Bits Per Pixel; and YUV 4:2:2)
- 256- × 24-Bit Entries Palette in RGB
- Up to 2048 × 2048 Resolution
- Display Support
- Four Types of Displays Are Supported: Passive and Active Colors; Passive and Active Monochromes
- 4- and 8-Bit Monochrome Passive Panel Interface Support (15 Grayscale Levels Supported Using Dithering Block)
- RGB 8-Bit Color Passive Panel Interface Support (3,375 Colors Supported for Color Panel Using Dithering Block)
- RGB 12-, 16-, 18-, and 24-Bit Active Panel Interface Support (Replicated or Dithered Encoded Pixel Values)
- Remote Frame Buffer (Embedded in the LCD Panel) Support Through the RFBI Module
- Partial Refresh of the Remote Frame Buffer Through the RFBI Module
- Partial Display
- Multiple Cycles Output Format on 8-, 9-, 12-, and 16-Bit Interface (TDM)
- Signal Processing
- Overlay and Windowing Support for One Graphics Layer (RGB or CLUT) and Two Video Layers (YUV 4:2:2, RGB16, and RGB24)
- RGB 24-Bit Support on the Display Interface, Optionally Dithered to RGB 18‑Bit Pixel Output Plus 6-Bit Frame Rate Control (Spatial and Temporal)
- Transparency Color Key (Source and Destination)
- Synchronized Buffer Update
- Gamma Curve Support
- Multiple-Buffer Support
- Cropping Support
- Color Phase Rotation
- Display Modes
- Two 12-Bit SAR ADCs (ADC0,
ADC1)
- 867K Samples Per Second
- Input Can Be Selected from Any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
- ADC0 Can Be Configured to Operate as a 4‑, 5-, or 8-Wire Resistive Touch Screen Controller (TSC)
- Up to Three 32-Bit eCAP Modules
- Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
- Up to Six Enhanced eHRPWM Modules
- Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
- Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
- Up to Three 32-Bit eQEP Modules
- Device Identification
- Factory Programmable Electrical Fuse Farm (FuseFarm)
- Production ID
- Device Part Number (Unique JTAG ID)
- Device Revision (Readable by Host ARM)
- Security Keys (Avaliable Only on AM437xHS Devices)
- Feature Identification
- Factory Programmable Electrical Fuse Farm (FuseFarm)
- Debug Interface Support
- JTAG and cJTAG for ARM (Cortex-A9 and PRCM) and PRU-ICSS Debug
- Supports Real-Time Trace Pins (for Cortex-A9)
- 64-KB Embedded Trace Buffer (ETB)
- Supports Device Boundary Scan
- Supports IEEE 1500
- DMA
- On-Chip Enhanced DMA Controller (EDMA) Has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels
- EDMA is Used for:
- Transfers to and from On-Chip Memories
- Transfers to and from External Storage (EMIF, GPMC, and Slave Peripherals)
- InterProcessor Communication (IPC)
- Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between the Cortex-A9, PRCM, and PRU-ICSS
- Boot Modes
- Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
- Camera
- Dual Port 8- and 10-Bit BT656 Interface
- Dual Port 8- and 10-Bit Including External Syncs
- Single Port 12-Bit
- YUV422/RGB422 and BT656 Input Format
- RAW Format
- Pixel Clock Rate up to 75 MHz
- Package
- 491-Pin BGA Package (17-mm × 17-mm) (ZDN Suffix), 0.65-mm Ball Pitch With Via Channel Array Technology to Enable Low-Cost Routing
The TI AM437x high-performance processors are based on the ARM Cortex-A9 core.
The processors are enhanced with 3D graphics acceleration for rich graphical user interfaces, as well as a coprocessor for deterministic, real-time processing including industrial communication protocols, such as EtherCAT, PROFIBUS, EnDat, and others. The devices support high-level operating systems (HLOS). Linux® is available free of charge from TI. Other HLOSs are available from TI’s Design Network and ecosystem partners.
These devices offer an upgrade to systems based on lower performance ARM cores and provide updated peripherals, including memory options such as QSPI-NOR and LPDDR2.
The processors contain the subsystems shown in the Functional Block Diagram, and a brief description of each follows.
The processor subsystem is based on the ARM Cortex-A9 core, and the PowerVR SGX™ graphics accelerator subsystem provides 3D graphics acceleration to support display and advanced user interfaces.
The programmable real-time unit subsystem and industrial communication subsystem (PRU-ICSS) is separate from the ARM core and allows independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, EnDat, and others. The PRU-ICSS enables EnDat and another industrial communication protocol in parallel. Additionally, the programmable nature of the PRU-ICSS, along with their access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in off-loading tasks from the other processor cores of the SoC.
High-performance interconnects provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals. The device also offers a comprehensive clock-management scheme.
One on-chip analog to digital converter (ADC0) can couple with the display subsystem to provide an integrated touch-screen solution. The other ADC (ADC1) can combine with the pulse width module to create a closed-loop motor control solution.
The RTC provides a clock reference on a separate power domain. The clock reference enables a battery-backed clock reference.
The camera interface offers configuration for a single- or dual-camera parallel port.
Cryptographic acceleration is available in all devices. All other supported security features, including support for Secure boot, debug security and support for Trusted execution environment is available on HS (High-Security) devices. For more information about HS devices, contact your TI sales representative.
技術文件
設計與開發
電源供應解決方案
為 AM4377 尋找可用的電源供應解決方案。TI 提供適用於 TI 與非 TI 之系統單晶片 (SoC)、處理器、微控制器、感測器或現場可編程邏輯閘陣列 (FPGA) 的電源供應解決方案。
TMDSEVM437X — AM437x 評估模組
AM437x 評估模組 (EVM) TMDXEVM437X 可讓開發人員立即開始評估 AM437x 處理器系列 (AM4372、AM4376、AM4377、AM4378)，並著手建置應用程式，以及加速開發 HMI、工業和網路應用。TMDSEVM437X 開發平台是以 Arm Cortex-A9 處理器為基礎，並與多個選項整合，例如 Gigabit 乙太網路、DDR3、2 個攝影機模組，以及 7" 電容式觸控螢幕 LCD 等。
TMDSIDK437X — AM437x/AMIC120 工業開發套件 (IDK)
AM437x/AMIC120 工業開發套件 (IDK) 是一個應用開發平台，可評估工業應用的 Sitara™ AM4379、AM4377 及 AMIC120 處理器之工業通訊和控制能力。
AM4379、AM4377 及 AMIC120 處理器適合工業通訊、工業控制及工業驅動等應用。AM437x 和 AMIC120 處理器整合四核心可編程即時單元 (PRU)，單元的架構可運用各種工業自動化設備中使用的即時通訊技術。其小體積的設計配備了最小外部元件和同級最佳的低功率效能。
目標應用
IDK 硬體和軟體專為工業應用設計：
- 工業驅動器
- 工業感測器和 I/O 單元
- 工業通訊閘道
- 具有整合式工業通訊 (如 (...)
TMDXSK437X — AM437x 入門套件
AM437x 入門套件提供穩定且經濟實惠的平台，可快速開始評估 Sitara™ Arm® Cortex®-A9 AM437x 處理器（AM4376、AM4378），並加速開發 HMI、工業及網路應用。這是以 ARM Cortex-A9 處理器為基礎的低成本開發平台，並整合多個選項，如雙 GB 乙太網路、DDR3L、攝影機和電容式觸控螢幕 LCD 等。
AM437x 入門套件能以高達 1GHz 的速度，透過可立即生產的硬體與軟體平台加速設計。這款「最佳價值」電路板可協助快速評估處理器功能與隨附 TI 元件，無需在設計硬體時進行臆測，讓資深和資淺的設計師都能專注在如先進繪圖與連線等產品差異化特質。
BYTES-3P-SITARASOMS — 工作位元組 Sitara SOM
Learn more about bytes at work at http://www.bytesatwork.io/en.
COMPU-3P-SITARASOMS — Compulab Sitara SOM
MISTR-3P-POM-AM437X — Mistral 解決方案 AM437x PoM 和應用電路板
SVT-3P-SITARA-SOMS — 用於 AM437x CPU 的 SVTronics 系統模組
VAR-3P-SITARASOMS — Variscite Sitara SOM
PRUCAPE — TI PRU Cape
TI PRU Cape 是 BeagleBone Black 附加電路板，可讓使用者了解 TI 強大的可編程即時單元 (PRU) 核心及基本功能。PRU 是整合在 Sitara AM335x 和 AM437x 裝置系列中的低延遲微控制器子系統。 PRU 核心針對確定性、即時處理、直接存取 I/O 與超低延遲需求進行最佳化。 它包括適用於 GPIO、音訊和溫度感測器的 LED 和按鈕。 BeagleBone Black 與 PRUCAPE 搭配使用，是在 Sitara 平台上開始進行 PRU 開發的理想 EVM 解決方案。
TMDSEMU200-U — XDS200 USB 偵錯探測器
XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器（模擬器）。對於大多數裝置，建議使用較新、成本較低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 支援單一 Pod 中廣泛的標準（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。
XDS200 透過 TI 20 接腳連接器（配備適用 TI 14 接腳、Arm Cortex® 10 接腳和 Arm 20 接腳的多重轉接器）連接到目標電路板，並透過 USB2.0 高速 (...)
TMDSEMU560V2STM-U — XDS560™ 軟體 v2 系統追蹤 USB 偵錯探測器
XDS560v2 是 XDS560™ 系列偵錯探測器中性能最高的，且同時支援傳統 JTAG 標準 (IEEE1149.1) 與 cJTAG (IEEE1149.7)。 請注意，其不支援序列線偵錯 (SWD)。
所有 XDS 偵錯探測器均在所有配備嵌入式追蹤緩衝器 (ETB) 的 ARM 與 DSP 處理器中支援核心與系統追蹤。 對於針腳上的追蹤，則需要 XDS560v2 PRO TRACE。
XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (...)
TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器
The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).
All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)
PROCESSOR-SDK-LINUX-AM437X — Linux processor SDK for AM437x
Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)
PROCESSOR-SDK-LINUX-RT-AM437X — Linux-RT Processor SDK for AM437x
Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)
PROCESSOR-SDK-RTOS-AM437X — TI-RTOS processor SDK for AM437x and AMIC120 (No design support from TI available. Refer to Overview- RTOS Highlights for details.)
Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)
PRU-SWPKG — Programmable Real-time Unit (PRU) Software Support Package
The PRU Software Support Package is an add-on package that provides a framework and examples for developing software for the Programmable Real-time Unit sub-system and Industrial Communication Sub-System (PRU-ICSS) in the supported TI processors. The PRU-ICSS achieves deterministic, real-time (...)
TIBLUETOOTHSTACK-SDK — TI 雙模式 Bluetooth® 堆疊
TI 的雙模式 Bluetooth 堆疊支援 Bluetooth + Bluetooth 低功耗，並包含實作 Bluetooth 4.0/4.1/4.2 規格的單模式與雙模式產品。Bluetooth 堆疊已完全通過 Bluetooth 技術聯盟 (SIG) 認證並免權利金，提供簡易的命令行範例應用程式以加速開發，並且根據需求提供 MFI 功能。
堆疊可與以下裝置配合使用：
- MSP432 (CC256XMS432BTBLESW)1
- MSP430 (CC256XMSPBTBLESW)1
- TM4C (CC256XM4BTBLESW)1
- 其他 MCU (CC256XSTBTBLESW)1
- Sitara ARM (...)
CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)
CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)
SYSCONFIG — Standalone desktop version of SysConfig
CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.
SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)
GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS
MG-3P-NUCLEUS-RTOS — Mentor Graphics Nucleus RTOS
QNX-3P-NEUTRINO-RTOS — QNX Neutrino RTOS
PRU-ICSS-ETHERCAT-SLAVE — PRU-ICSS software for EtherCAT slave
PRU-ICSS 通訊協定為 TI Sitara 處理器實現即時工業通訊。 PRU-ICSS 通訊協定可在 Processor-SDK-RTOS、TI 的統合軟體開發平台上使用，並且包含最佳化 PRU-ICSS 韌體，這是適用於 ARM 處理器及範例應用的對應 PRU-ICSS 驅動程式。PRU-ICSS 韌體在 PRU 核心上運作，將時間關鍵的鏈路層處理從運作 TI-RTOS 的主 ARM 處理器中卸載。PRU-ICSS 驅動程式為 PRU-ICSS 資源提供了簡單的存取方式，並能輕鬆與在 ARM 核心上運作的通訊協定堆疊和應用程式軟體整合。 (...)
PRU-ICSS-ETHERNETIP-ADAPTER — PRU-ICSS software for EtherNetIP adapter
PRU-ICSS 通訊協定為 TI Sitara 處理器實現即時工業通訊。 PRU-ICSS 通訊協定可在 Processor-SDK-RTOS、TI 的統合軟體開發平台上使用，並且包含最佳化 PRU-ICSS 韌體，這是適用於 ARM 處理器及範例應用的對應 PRU-ICSS 驅動程式。PRU-ICSS 韌體在 PRU 核心上運作，將時間關鍵的鏈路層處理從運作 TI-RTOS 的主 ARM 處理器中卸載。PRU-ICSS 驅動程式為 PRU-ICSS 資源提供了簡單的存取方式，並能輕鬆與在 ARM 核心上運作的通訊協定堆疊和應用程式軟體整合。 (...)
PRU-ICSS-HSR-PRP-DAN — PRU-ICSS software for HSR/PRP
PRU-ICSS 通訊協定為 TI Sitara 處理器實現即時工業通訊。 PRU-ICSS 通訊協定可在 Processor-SDK-RTOS、TI 的統合軟體開發平台上使用，並且包含最佳化 PRU-ICSS 韌體，這是適用於 ARM 處理器及範例應用的對應 PRU-ICSS 驅動程式。PRU-ICSS 韌體在 PRU 核心上運作，將時間關鍵的鏈路層處理從運作 TI-RTOS 的主 ARM 處理器中卸載。PRU-ICSS 驅動程式為 PRU-ICSS 資源提供了簡單的存取方式，並能輕鬆與在 ARM 核心上運作的通訊協定堆疊和應用程式軟體整合。 (...)
PRU-ICSS-INDUSTRIAL-DRIVES — PRU-ICSS software for industrial drives (EnDat2.2, Tamagawa, Hiperface DSL,SDDF and motor control support)
PRU-ICSS 通訊協定為 TI Sitara 處理器實現即時工業通訊。 PRU-ICSS 通訊協定可在 Processor-SDK-RTOS、TI 的統合軟體開發平台上使用，並且包含最佳化 PRU-ICSS 韌體，這是適用於 ARM 處理器及範例應用的對應 PRU-ICSS 驅動程式。PRU-ICSS 韌體在 PRU 核心上運作，將時間關鍵的鏈路層處理從運作 TI-RTOS 的主 ARM 處理器中卸載。PRU-ICSS 驅動程式為 PRU-ICSS 資源提供了簡單的存取方式，並能輕鬆與在 ARM 核心上運作的通訊協定堆疊和應用程式軟體整合。 (...)
PRU-ICSS-PROFIBUS-SLAVE — PRU-ICSS software for PROFIBUS slave
PRU-ICSS 通訊協定為 TI Sitara 處理器實現即時工業通訊。 PRU-ICSS 通訊協定可在 Processor-SDK-RTOS、TI 的統合軟體開發平台上使用，並且包含最佳化 PRU-ICSS 韌體，這是適用於 ARM 處理器及範例應用的對應 PRU-ICSS 驅動程式。PRU-ICSS 韌體在 PRU 核心上運作，將時間關鍵的鏈路層處理從運作 TI-RTOS 的主 ARM 處理器中卸載。PRU-ICSS 驅動程式為 PRU-ICSS 資源提供了簡單的存取方式，並能輕鬆與在 ARM 核心上運作的通訊協定堆疊和應用程式軟體整合。 (...)
PRU-ICSS-PROFINET-SLAVE — PRU-ICSS software for Profinet slave
PRU-ICSS 通訊協定為 TI Sitara 處理器實現即時工業通訊。 PRU-ICSS 通訊協定可在 Processor-SDK-RTOS、TI 的統合軟體開發平台上使用，並且包含最佳化 PRU-ICSS 韌體，這是適用於 ARM 處理器及範例應用的對應 PRU-ICSS 驅動程式。PRU-ICSS 韌體在 PRU 核心上運作，將時間關鍵的鏈路層處理從運作 TI-RTOS 的主 ARM 處理器中卸載。PRU-ICSS 驅動程式為 PRU-ICSS 資源提供了簡單的存取方式，並能輕鬆與在 ARM 核心上運作的通訊協定堆疊和應用程式軟體整合。 (...)
WIND-3P-VXWORKS-LINUX-OS — Wind River 處理器 VxWorks 和 Linux 作業系統
Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)
WIT-3P-SITARABSP — Witekio Sitara Android 和 Windows 作業系統
SITARA-DDR-CONFIG-TOOL-AM335X — AM335x and AMIC110 EMIF Tools
Sitara™ EMIF 工具是一款軟體工具，提供配置 TI 處理器以存取外部 DDR 記憶體裝置的介面。該工具還最佳化延遲鎖定迴路 (DLL) 設定，以補償電路板佈線偏斜。結果輸出為 EMIF 配置暫存器，可導入以在處理器 SDK、Code Composer Studio 或自訂軟體中使用。
UNIFLASH — UniFlash for most TI microcontrollers (MCUs) and mmWave sensors
UniFlash 是 TI 龐大 CCStudio™ 開發生態系統的一部分，是一款用於在 TI 微控制器與無線連線裝置上對晶片內快閃記憶體進行燒錄，以及在 TI 處理器上對板載快閃記憶體進行燒錄的軟體工具。UniFlash 提供圖形化介面與命令行介面，並可在桌面上或雲端中執行。
UniFlash 可從 CCStudio™ 開發人員區上的雲端執行，或在下載後於 Windows®、Linux® 和 macOS® 電腦中使用。
請注意，mmWave、AMx、K2G 和 J7 裝置不支援 macOS。AMx、K2G 和 J7 裝置僅於命令列上支援。
AUTOMATA-3P-INDUSTRIALCOMMS — Cannon Automata Sercos III
CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具
The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
- Visualize the device clock tree
- Interact with clock tree (...)
POWEREST — 功率估計工具 (PET)
功耗估算工具 (PET) 讓使用者能深入瞭解特定 TI 處理器的功耗情況。本工具允許使用者選擇多種應用場景，不僅能掌握功耗數據，更能理解如何運用進階節能技術進一步降低整體功耗。
AM57x 與 AM437x 處理器專用 PET：
此可下載試算表提供使用者輸入應用所需裝置參數的機制。參數包含 IP 模組活動狀態/負載量、目標電源模式及電源管理使用情境。可設定多重運作條件並為每種狀態配置時間區段。電源估算數據已內嵌於試算表中，所有結果將直接在試算表內自動生成（無需上傳任何資料）。
AM57x 專用 PET：
(...)
SITARA-DDR-CONFIG-TOOL-AM65X-DRA80XM — AM65x/DRA80xM EMIF 工具試算表
Sitara™ EMIF 工具是一款軟體工具，提供配置 TI 處理器以存取外部 DDR 記憶體裝置的介面。該工具還最佳化延遲鎖定迴路 (DLL) 設定，以補償電路板佈線偏斜。結果輸出為 EMIF 配置暫存器，可導入以在處理器 SDK、Code Composer Studio 或自訂軟體中使用。
許多 TI 參考設計包含 AM4377
使用我們的參考設計選擇工具，以檢視並找出最適合您的應用和參數的設計。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| NFBGA (ZDN) | 491 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。