產品詳細資料

CPU 1 Arm Cortex-A53, 2 Arm Cortex-A53 Frequency (MHz) 1250 Display type 1 DSI, MIPI DPI Protocols Ethernet, TSN Hardware accelerators CPU only Features General purpose Operating system Linux Security Secure boot Rating Catalog Power supply solution TPS65214 Operating temperature range (°C) -40 to 125 Edge AI enabled Yes
CPU 1 Arm Cortex-A53, 2 Arm Cortex-A53 Frequency (MHz) 1250 Display type 1 DSI, MIPI DPI Protocols Ethernet, TSN Hardware accelerators CPU only Features General purpose Operating system Linux Security Secure boot Rating Catalog Power supply solution TPS65214 Operating temperature range (°C) -40 to 125 Edge AI enabled Yes
FCCSP (ANB) 373 141.6 mm² 11.8 x 12

Processor Cores:

  • Dual 64-bit Arm Cortex-A53 microprocessor subsystem up to 1.25GHz
    • Dual-core Cortex-A53 with 256KB L2 Cache
    • Each A53 core has 32KB L1 DCache and 32KB L1 ICache

Memory Subsystem:

  • 160KB of Shared On-Chip SRAM (OCSRAM)
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-bit data bus
    • Supports speeds up to 1600MT/s
    • Max DDR4 addressing range of 4GB
    • Max LPDDR4 addressing range of 2GB

Multimedia:

  • Display Subsystem
    • Single display support
    • Up to 1920x1080 @ 60fps
    • Supported with independent PLL
    • MIPI DSI (4 lanes DPHY) or DPI (24-bit RGB LVCMOS)

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES – 128-/192-/256-bit key sizes
      • SHA2 – 224-/256-/384-/512-bit key sizes
      • DRBG with true random number generator
      • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High Speed Interfaces:

  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Priority based flow control
    • Packet Classifier based on ALE engine with 64 classifiers
    • Time sensitive networking (TSN) support
    • H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • 2× USB 2.0 Dual-Role Device (DRD) Subsystems (USBSS)
    • Port configurable as USB host or USB device
    • USB device: High-speed (480Mbps), and Full-speed (12Mbps)
    • USB host: High-speed (480Mbps), Full-speed (12Mbps), and Low-speed (1.5Mbps)
    • xHCI 1.1 compatible

General Connectivity:

  • 8x Universal Asynchronous Receiver-Transmitters (UARTs)
    • All instances Support RTS and CTS Flow Control
    • Supports RS-485 external transceiver auto flow control
  • 4x Serial Peripheral Interface (SPI) controllers
  • 5x Inter-Integrated Circuit (I2C) ports
  • 3x Multichannel Audio Serial Ports (McASPs)
    • Transmit and Receive clocks up to 50MHz
    • Up to 4/6/16 Serial Data Pins across 3x McASPs with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and similar formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 formats)
    • FIFO buffers for Transmit and Receive (256Bytes)
    • Support for audio reference output clock
  • 3x enhanced PWM modules (ePWM)
  • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
  • 3x enhanced Capture modules (eCAP)
  • General-Purpose I/O (GPIO), most LVCMOS I/O can be configured as GPIO
    • 4 banks supported for dual-voltage (1.8V/3.3V) and the rest single-voltage (1.8V) LVCMOS I/O banks
  • 3x Controller Area Network (CAN) with optional CAN-FD support
    • Conforms with CAN Protocol 2.0 A, B, and ISO 11898-1
    • Full CAN-FD support (up to 64 data bytes)
    • Speed up to 8Mbps
  • 1x 12-bit Analog-to-Digital Converter (ADC)
    • 10 bits of effective resolution (ENOB ≅ 10)
    • Up to 2MSPS
    • 4x analog inputs (time-multiplexed)

Media and Data Storage:

  • 3x Multi-Media Card/Secure Digital (MMC/SD) interface
    • 1x 8-bit eMMC interface up to HS200 speed
    • 2x 4-bit SD/SDIO interface up to UHS-I
    • Compliant with eMMC 5.1, SD 3.01, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
    • Flexible 8- and 16-Bit Synchronous or Asynchronous Memory Interfaces with up to four Chip Selects
    • Supports 16-bit Muxed Address/Data schemes (AD, AAD)
    • Uses BCH code to support 4-, 8-, or 16-bit ECC
    • Uses Hamming code to support 1-bit ECC
    • Error Locator Module (ELM)
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash devices
    • 4GBytes memory address support

Power Management:

  • Active power management features such as auto clock gating, power gating, and dynamic frequency scaling
  • Several low-power features supported
  • Low-Power Modes
    • RTC Only
    • RTC + IO + DDR
    • DeepSleep
    • Standby

Boot Options:

  • UART
  • OSPI/QSPI Flash
  • GPMC NAND Flash
  • SD Card
  • eMMC
  • USB (host) Mass storage
  • USB (device) boot from external host (DFU mode)

Technology / Package:

  • 16-nm Technology
  • 11.9mm × 11.9mm, 0.5mm VCA, 373-pin FCCSP BGA package (ANB)

Processor Cores:

  • Dual 64-bit Arm Cortex-A53 microprocessor subsystem up to 1.25GHz
    • Dual-core Cortex-A53 with 256KB L2 Cache
    • Each A53 core has 32KB L1 DCache and 32KB L1 ICache

Memory Subsystem:

  • 160KB of Shared On-Chip SRAM (OCSRAM)
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-bit data bus
    • Supports speeds up to 1600MT/s
    • Max DDR4 addressing range of 4GB
    • Max LPDDR4 addressing range of 2GB

Multimedia:

  • Display Subsystem
    • Single display support
    • Up to 1920x1080 @ 60fps
    • Supported with independent PLL
    • MIPI DSI (4 lanes DPHY) or DPI (24-bit RGB LVCMOS)

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES – 128-/192-/256-bit key sizes
      • SHA2 – 224-/256-/384-/512-bit key sizes
      • DRBG with true random number generator
      • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High Speed Interfaces:

  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Priority based flow control
    • Packet Classifier based on ALE engine with 64 classifiers
    • Time sensitive networking (TSN) support
    • H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • 2× USB 2.0 Dual-Role Device (DRD) Subsystems (USBSS)
    • Port configurable as USB host or USB device
    • USB device: High-speed (480Mbps), and Full-speed (12Mbps)
    • USB host: High-speed (480Mbps), Full-speed (12Mbps), and Low-speed (1.5Mbps)
    • xHCI 1.1 compatible

General Connectivity:

  • 8x Universal Asynchronous Receiver-Transmitters (UARTs)
    • All instances Support RTS and CTS Flow Control
    • Supports RS-485 external transceiver auto flow control
  • 4x Serial Peripheral Interface (SPI) controllers
  • 5x Inter-Integrated Circuit (I2C) ports
  • 3x Multichannel Audio Serial Ports (McASPs)
    • Transmit and Receive clocks up to 50MHz
    • Up to 4/6/16 Serial Data Pins across 3x McASPs with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and similar formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 formats)
    • FIFO buffers for Transmit and Receive (256Bytes)
    • Support for audio reference output clock
  • 3x enhanced PWM modules (ePWM)
  • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
  • 3x enhanced Capture modules (eCAP)
  • General-Purpose I/O (GPIO), most LVCMOS I/O can be configured as GPIO
    • 4 banks supported for dual-voltage (1.8V/3.3V) and the rest single-voltage (1.8V) LVCMOS I/O banks
  • 3x Controller Area Network (CAN) with optional CAN-FD support
    • Conforms with CAN Protocol 2.0 A, B, and ISO 11898-1
    • Full CAN-FD support (up to 64 data bytes)
    • Speed up to 8Mbps
  • 1x 12-bit Analog-to-Digital Converter (ADC)
    • 10 bits of effective resolution (ENOB ≅ 10)
    • Up to 2MSPS
    • 4x analog inputs (time-multiplexed)

Media and Data Storage:

  • 3x Multi-Media Card/Secure Digital (MMC/SD) interface
    • 1x 8-bit eMMC interface up to HS200 speed
    • 2x 4-bit SD/SDIO interface up to UHS-I
    • Compliant with eMMC 5.1, SD 3.01, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
    • Flexible 8- and 16-Bit Synchronous or Asynchronous Memory Interfaces with up to four Chip Selects
    • Supports 16-bit Muxed Address/Data schemes (AD, AAD)
    • Uses BCH code to support 4-, 8-, or 16-bit ECC
    • Uses Hamming code to support 1-bit ECC
    • Error Locator Module (ELM)
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash devices
    • 4GBytes memory address support

Power Management:

  • Active power management features such as auto clock gating, power gating, and dynamic frequency scaling
  • Several low-power features supported
  • Low-Power Modes
    • RTC Only
    • RTC + IO + DDR
    • DeepSleep
    • Standby

Boot Options:

  • UART
  • OSPI/QSPI Flash
  • GPMC NAND Flash
  • SD Card
  • eMMC
  • USB (host) Mass storage
  • USB (device) boot from external host (DFU mode)

Technology / Package:

  • 16-nm Technology
  • 11.9mm × 11.9mm, 0.5mm VCA, 373-pin FCCSP BGA package (ANB)

The low-cost & performance optimized AM62L family of application processors are built for Linux application development. With scalable Arm Cortex-A53 core performance and embedded features such as: Multimedia DSI/DPI support, integrated ADC on chip, advanced lower power management modes, and extensive security options for IP protection with the built-in security features.

The AM62Lx devices includes an extensive set of peripherals that make it a well-suited general-purpose device for a broad range of industrial applications while offering intelligent features and optimized power architecture as well. In addition, the extensive set of peripherals included in AM62Lx enables system-level connectivity, such as: USB, MMC/SD, OSPI, CAN-FD and an ADC.

The low-cost & performance optimized AM62L family of application processors are built for Linux application development. With scalable Arm Cortex-A53 core performance and embedded features such as: Multimedia DSI/DPI support, integrated ADC on chip, advanced lower power management modes, and extensive security options for IP protection with the built-in security features.

The AM62Lx devices includes an extensive set of peripherals that make it a well-suited general-purpose device for a broad range of industrial applications while offering intelligent features and optimized power architecture as well. In addition, the extensive set of peripherals included in AM62Lx enables system-level connectivity, such as: USB, MMC/SD, OSPI, CAN-FD and an ADC.

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技術文件

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重要文件 類型 標題 格式選項 日期
* Data sheet AM62Lx Sitara™ Processors datasheet (Rev. B) PDF | HTML 2025年 11月 30日
* Errata AM62Lx Sitara Processors Silicon Errata (Rev. B) PDF | HTML 2025年 10月 7日
* User guide AM62L Technical Reference Manual (Rev. A) 2025年 9月 30日
Application note Throughput Characterization of OSPI and QSPI Serial NOR/NAND Flash Operations PDF | HTML 2026年 2月 17日
User guide Hardware Design Considerations for Custom Board Design Using AM62L (AM62L32, AM62L31) Family of Processors (Rev. B) PDF | HTML 2026年 1月 27日
User guide AM62L Power Visualizer User's Guide PDF | HTML 2025年 12月 5日
Application note Convert Sitara MPU HS-FS Silicon to HS-SE with No Boot Mode Switch PDF | HTML 2025年 12月 5日
Application note Enabling Matter on Sitara MPU (Rev. A) PDF | HTML 2025年 11月 24日
Application note Thermal Management of TDA4x and AM6x PDF | HTML 2025年 10月 30日
Application note AM62L Power Consumption Summary PDF | HTML 2025年 10月 20日
Application note Sitara Processor Power Distribution Networks: Implementation and Analysis (Rev. H) PDF | HTML 2025年 10月 17日
Application note AM62Lx Power Supply Implementation (Rev. B) PDF | HTML 2025年 10月 10日
Application note AM625x/AM623x and AM62Lx Hardware Migration Guide PDF | HTML 2025年 10月 6日
Application note AM62L Power Estimation Tool PDF | HTML 2025年 9月 22日
Application note AM62x, AM62Ax, AM62Px, AM62Lx Spread-Spectrum Clocking PDF | HTML 2025年 9月 8日
Application note Custom Board Design and Simulation Guidelines for Processor High Speed Parallel Interfaces (Rev. A) PDF | HTML 2025年 9月 5日
Application note Processors Tools Overview PDF | HTML 2025年 6月 16日
Application note Sitara™AM62Lx Benchmarks PDF | HTML 2025年 3月 10日
Application note AM62x, AM62Lx DDR Board Design and Layout Guidelines (Rev. C) PDF | HTML 2025年 3月 5日
Application brief AM62L Maximum Current Ratings PDF | HTML 2025年 3月 4日
User guide AM62L (AM62L32, AM62L31) Processor Family Schematic Design Guidelines and Schematic Review Checklist PDF | HTML 2025年 3月 3日
Product overview AM62L - Low Power Cortex A53 SoC for Cost Optimized IOT, HMI, and General-Purpose Applications PDF | HTML 2025年 3月 3日
Application brief Growing Need of Processing Technologies in Smart E - Meters PDF | HTML 2025年 2月 21日
Application note AM62Lx Escape Routing Guidelines PDF | HTML 2024年 3月 26日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

TMDS62LEVM — AM62L 評估模組

TMDS62LEVM 評估模組 (EVM) 專為低成本與效能最佳化 AM62L 應用處理器系列而設計。AM62L 具有可擴充的 Arm® Cortex® A53 核心效能和嵌入式功能,例如:多媒體 DSI 支援,整合式晶片 ADC ,進階低功耗管理模式,以及用於 IP 保護和安全啟動的廣泛安全選項。AM62L 系列裝置支援使用 Linux® 和 FreeRTOS ™ 進行開發。TMDS62LEVM 包含各種周邊裝置,非常適合用於各種工業應用的通用裝置,同時也提供智慧功能與最佳電源架構。此外, AM62L 中包含的多種周邊裝置可實現系統級連線,例如:USB , MMC/SD , OSPI , (...)
使用指南: PDF
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開發板

IWAVE-3P-OSM-LF-AM62LX — iWave Global TI AM62Lx OSM Size-S System on Module

iWave’s iG-RainboW-G69M OSM Size-SF System on Module integrates the TI AM62Lx SoC featuring dual 64-bit Arm® Cortex®-A53 cores running up to 1.25GHz. Built on the OSM v1.2 standard with a compact 30mm x 30mm LGA form factor, it supports 1GB LPDDR4 (expandable to 2GB), 8GB eMMC (expandable), and (...)

子卡

AM62L-EVSE-DEV-EVM — AM62L EVSE 評估模組

AM62L-EVSE-DEV-EVM 是 AM62L 的 TI-EVSE 開發平台的一部分,針對交流電與直流電充電站提供支援開放原始碼軟體堆疊的通用充電控制器。完整的平台由三個獨立零件組成:AM62L EVM (TMDS62LEVM)、AM62L- EVSE-DEV-EVM 和 TIDA-010239(選配)。

TMDS62LEVM 作為主要 CPU,支援乙太網路和無線連線通訊。AM62L-EVSE-DEV-EVM 則作為前端控制器,控制與電動車之間的類比握手訊號,以及鎖定充電插頭和監控高電壓接點內部溫度等安全功能。如果想增加交流電充電功能,還可以加裝選配的 TIDA-010239。

使用指南: PDF | HTML
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偵錯探測器

TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器(模擬器)。對於大多數裝置,建議使用較新、成本較低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 支援單一 Pod 中廣泛的標準(IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。

XDS200 透過 TI 20 接腳連接器(配備適用 TI 14 接腳、Arm Cortex® 10 接腳和 Arm 20 接腳的多重轉接器)連接到目標電路板,並透過 USB2.0 高速 (...)

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偵錯探測器

LB-3P-TRACE32-ARM — 適用於 Arm® 架構微控制器和處理器的 Lauterbach TRACE32® 偵錯和追蹤系統

Lauterbach 的 TRACE32® 工具是一套先進的軟硬體元件,可讓開發人員分析、最佳化及認證各種 Arm® 架構微控制器和處理器。全球知名的嵌入式系統和 SoC 偵錯和追蹤解決方案是完美的解決方案,適用於從早期的矽前 (pre-silicon) 開發,到產品認證和現場故障排除等所有開發階段。Lauterbach 工具的直覺模組化設計為工程師提供現今最高的可用性能,以及可隨需求變化而調整和成長的系統。藉由 TRACE32® 偵錯器,開發人員也可透過單一偵錯介面,同時偵錯和控制 SoC 中的任何 C28x/C29x/C6x/C7x DSP 核心及所有其他 Arm (...)

軟體開發套件 (SDK)

AM62L-FREERTOS-SDK FreeRTOS SDK for AM62L family of devices

The AM62L processor Linux® and TI FreeRTOS software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across TI's broad portfolio for which they are (...)

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瀏覽 下載選項
軟體開發套件 (SDK)

AM62L-LINUX-RT-SDK Linux RT SDK for AM62L family of devices

The AM62L processor Linux® and TI FreeRTOS software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across TI's broad portfolio for which they are (...)

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軟體開發套件 (SDK)

AM62L-LINUX-SDK Linux SDK for AM62L family of devices

The AM62L processor Linux® and TI FreeRTOS software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across TI's broad portfolio for which they are (...)

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快速入門

TI-DEVELOPER-ZONE Start embedded development on your desktop or in the cloud

From evaluation to deployment the TI Developer Zone provides a comprehensive range of software, tools and training to ensure that you have everything you need for each stage of the development process.
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支援產品和硬體

IDE、配置、編譯器或偵錯程式

CCSTUDIO Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development tool ecosystem. It is an integrated development environment (IDE) for TI's microcontrollers, processors, wireless connectivity devices and radar sensors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize (...)

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IDE、配置、編譯器或偵錯程式

CLOCKTREE-AM62L Clock tree configuration for AM62L


The Clock Tree Tool (CTT) for ARM Processors & Digital Signal Processors is an interactive configuration software tool that provides information about device clock tree architecture. This tool allows visualization of the device clock tree. It can also be used to determine the exact register (...)

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IDE、配置、編譯器或偵錯程式

SYSCONFIG Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

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線上培訓

AM62L-ACADEMY AM62Lx Academy

AM62Lx Academy is designed to simplify and accelerate custom AM62Lx development.
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作業系統 (OS)

TRZN-3P-TORIZON-OS — Torizon OS 開箱即用的工業級嵌入式 Linux 發行版

Torizon OS 是一個免費的開放原始碼工業級嵌入式 Linux 作業系統,致力於簡化需要高可靠性和安全性的產品的開發和維護。除其他重要服務外,它還具備優化的容器執行時和可實現安全的離綫與遠程無線 (OTA) 更新,裝置監控和遠程存取的元件。Torizon OS 能透過簡單的客製化在您的硬體上直接使用,並預設為安全狀態,提供頻繁的更新和易於操作的簡易安全功能。Torizon OS 基於開放式軟體,沒有鎖定,完全免費,包括 Toradex 系統模組 (SoM) 的頻繁更新。利用 Torizon OS 簡化開發和網路安全合規性。
從:Torizon
作業系統 (OS)

WHIS-3P-SAFERTOS — WITTENSTEIN SAFERTOS 預先認證的安全 RTOS

SAFERTOS® 是專為嵌入式處理器設計的獨特即時作業系統。經 TÜV SÜD 預先認證,符合 IEC 61508 SIL3 與 ISO 26262 ASILD 標準。SAFERTOS® 是由 WHIS 專家團隊專為安全而打造,適用於全球重要安全應用。WHIS 與德州儀器的合作已經超過十年。在此期間,WHIS 已將 SAFERTOS® 移植至各種 TI 處理器,支援所有熱門核心,並可依要求提供其他架構。SAFERTOS® 專為您的特定處理器/編譯器組合量身打造,隨附完整的原始程式碼與設計保證包,可完全一目了然整個設計生命週期。許多 WHIS 客戶開始使用 FreeRTOS (...)
模擬型號

AM62L IBIS Model

SPRM861.ZIP (2037 KB) - IBIS Model
模擬型號

AM62L IBIS-AMI Model

SPRM868.ZIP (39973 KB) - IBIS-AMI Model
模擬型號

AM62Lx BSDL Model

SPRM858.ZIP (8 KB) - BSDL Model
模擬型號

AM62Lx Thermal Model

SPRM859.ZIP (1 KB) - Thermal Model
計算工具

AM62L-PET-CALC AM62L Power Estimation Tool

AM62L PET provides power consumption estimates based on measured and simulated data; they are provided “as is” and are not guaranteed within a specified precision.
支援產品和硬體

支援產品和硬體

參考設計

TIDA-010939 — 電動車供電設備前端控制器參考設計

此參考設計為電動車供電設備 (EVSE) 前端控制器,可做為 EV 充電程序的中央通訊模組使用。此設計支援 AC 和各種全球 DC 充電標準,包括組合充電系統 (CCS)、Guobiao/Tuijian (GB/T) 以及 Charge de Move (CHAdeMO)。
Design guide: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCCSP (ANB) 373 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

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若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

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