SDAA517 August   2026 AM620-Q1 , AM623 , AM625-Q1 , AM62A1-Q1 , AM62A3-Q1 , AM62A7-Q1 , AM62D-Q1 , AM62L , AM62P-Q1 , DRA821U-Q1 , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VP-Q1 , TDA4VPE-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1 ECC Error Logging Overview
      1. 2.1.1 Understanding ERR_ADR and ERR_MSK
    2. 2.2 Why Address Decoding is Required
    3. 2.3 DDR Inline ECC Memory Layout
      1. 2.3.1 TDA4VM / TDA4VE / TDA4VH
      2. 2.3.2 DRA821 / DRA829 / TDA4VEN / AM62A / AM62P
      3. 2.3.3 AM62 / AM62L / AM64
    4. 2.4 Address Decoding Methodology
    5. 2.5 AM62A Decoding Example
    6. 2.6 TDA4VE Dual-DDR Interleave Example
    7. 2.7 Decode Tool Usage
  6. 3Summary
  7. 4References
Application Note

DDR Inline ECC Error Address Decoding on Jacinto 7 and Sitara Processors