CD4021B-Q1
- Qualified for Automotive Applications
- Medium-Speed Operation: 12-MHz (Typ) Clock Rate at VDD – VSS = 10 V
- Fully Static Operation
- Eight Master-Slave Flip-Flops Plus Output Buffering and Control Gating
- 100% Tested for Quiescent Current at 20 V
- Maximum Input Current of 1 µA at 18 V Over Full Package-Temperature Range:
100 nA at 18 V and 25°C - Noise Margin (Full Package-Temperature Range):
- 1 V at VDD = 5 V
- 2 V at VDD = 10 V
- 2.5 V at VDD = 15 V
- Standardized Symmetrical Output Characteristics
- 5-V, 10-V, and 15-V Parametric Ratings
- Meets All Requirements of JEDEC Tentative Standard No. 13B,
"Standard Specifications for Description of ’B’ Series CMOS Devices" - Latch-Up Performance Meets 50 mA per JESD 78, Class I
- APPLICATIONS
- Parallel Input/Serial Output Data Queuing
- Parallel-to-Serial Data Conversion
- General-Purpose Register
CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is a D-type, master-slave flip-flop. In addition to an output from stage 8, "Q" outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014B. In the CD4021B serial entry is synchronous with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021B, the CLOCK input of the internal stage is "forced" when asynchronous parallel entry is made. Register expansion using multiple packages is permitted.
The CD4021B series types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CD4021B-Q1 CMOS 8-Stage Static Shift Register datasheet | 2010年 3月 26日 | |
| Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022年 12月 15日 | |
| Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
| More literature | Automotive Logic Devices Brochure | 2014年 8月 27日 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
| User guide | Signal Switch Data Book (Rev. A) | 2003年 11月 14日 | ||
| Application note | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | 2001年 12月 3日 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 引腳 | 下載 |
|---|---|---|
| SOIC (D) | 16 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點