產品詳細資料

Function Counter Bits (#) 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 125 Rating HiRel Enhanced Product
Function Counter Bits (#) 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 125 Rating HiRel Enhanced Product
SOIC (D) 16 59.4 mm² 9.9 x 6
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –40°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • Synchronous or Asynchronous Preset
  • Cascadable in Synchronous or Ripple Mode
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . 15 LSTTL Loads
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • VCC Voltage = 2 V to 6 V
  • High Noise Immunity NIL or NIH = 30% of VCC, VCC = 5 V

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –40°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • Synchronous or Asynchronous Preset
  • Cascadable in Synchronous or Ripple Mode
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . 15 LSTTL Loads
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • VCC Voltage = 2 V to 6 V
  • High Noise Immunity NIL or NIH = 30% of VCC, VCC = 5 V

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The CD74HC40103 is manufactured with high-speed silicon-gate technology and consists of an 8-stage synchronous down counter with a single output, which is active when the internal count is zero. The device contains a single 8-bit binary counter. Each device has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count (TC)\ output are active-low logic.

In normal operation, the counter is decremented by one count on each positive transition of the clock (CP) output. Counting is inhibited when the terminal enable (TE)\ input is high. TC\ goes low when the count reaches zero, if TE\ is low, and remains low for one full clock period.

When the synchronous preset enable (PE)\ input is low, data at the P0-P7 inputs are clocked into the counter on the next positive clock transition, regardless of the state of TE\. When the asynchronous preset enable (PL)\ input is low, data at the P0-P7 inputs asynchronously are forced into the counter, regardless of the state of the PE\, TE\, or CP inputs. Inputs P0-P7 represent a single 8-bit binary word for the CD74HC40103. When the master reset (MR)\ input is low, the counter asynchronously is cleared to its maximum count of 25510, regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table.

If all control inputs except TE\ are high at the time of zero count, the counters jump to the maximum count, giving a counting sequence of 10016 or 25610 clock pulses long.

The CD74HC40103 may be cascaded using the TE\ input and the TC\ output in either synchronous or ripple mode. These circuits have the low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low-power Schottky TTL circuits and can drive up to ten LSTTL loads.

The CD74HC40103 is manufactured with high-speed silicon-gate technology and consists of an 8-stage synchronous down counter with a single output, which is active when the internal count is zero. The device contains a single 8-bit binary counter. Each device has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count (TC)\ output are active-low logic.

In normal operation, the counter is decremented by one count on each positive transition of the clock (CP) output. Counting is inhibited when the terminal enable (TE)\ input is high. TC\ goes low when the count reaches zero, if TE\ is low, and remains low for one full clock period.

When the synchronous preset enable (PE)\ input is low, data at the P0-P7 inputs are clocked into the counter on the next positive clock transition, regardless of the state of TE\. When the asynchronous preset enable (PL)\ input is low, data at the P0-P7 inputs asynchronously are forced into the counter, regardless of the state of the PE\, TE\, or CP inputs. Inputs P0-P7 represent a single 8-bit binary word for the CD74HC40103. When the master reset (MR)\ input is low, the counter asynchronously is cleared to its maximum count of 25510, regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table.

If all control inputs except TE\ are high at the time of zero count, the counters jump to the maximum count, giving a counting sequence of 10016 or 25610 clock pulses long.

The CD74HC40103 may be cascaded using the TE\ input and the TC\ output in either synchronous or ripple mode. These circuits have the low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low-power Schottky TTL circuits and can drive up to ten LSTTL loads.

下載 觀看有字幕稿的影片 影片

您可能會感興趣的類似產品

open-in-new 比較替代產品
功能與所比較的裝置相似
SN74LV393B-EP 現行 增強型產品雙路四位元二進位計數器 Voltage range (2V to 5.5V), average drive strength (12mA), average propagation delay (9ns)

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 16
類型 標題 日期
* Data sheet CD74HC40103-EP datasheet 2003年 12月 4日
* Radiation & reliability report CD74HC40103QM96EP Reliability Report 2016年 8月 9日
* VID CD74HC40103-EP VID V6204702 2016年 6月 21日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 1996年 5月 1日
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (D) 16 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片